直接順序之分散式頻譜通訊系統設計

Abstract

在本論文中,利用 OPUS 這套積體電路設計環境下,我們使用0.8微米 CMOS 全數位積體電路技術來實現BPSK直接順序之分散式頻譜通訊系統.這 個架構包括基頻發射器同調中頻(IF)接收器,在接收器中,又可分為解調電 路,搜尋 PN 碼電路和鎖相電路,在系統中最大的中頻(IF)取樣頻率為 50.8 MHz,最大的 PN 碼頻率為 12.7 MHz,且可接 100,200,400 Kps三種 不同的信號輸入頻率. This thesis describes a fully integrated digital BPSK DS spread spectrum transceiver chip fabricated through SPDM in 0.8 um CMOS. The design of a binary-phase shift-keyed (BPSK) spread spectrum chip set with an integrated CAD environment called OPUS The architecture includes a baseband spread spectrum transmitter and a coherent intermediate frequence(IF)receiver consisting of a demodulation loop,an acquisition loop for the pseudo-noise(PN) sequence, and a clock tracking loop. The transceiver is capable of operation at a maximum IF sampling rate of 50.8 MHz and a maximum chip rate of 12.7 MHz with selectable data rate of 100, 200, 400 Kbps.