高性能的放大器與比較器之設計

Abstract

本論文將介紹運用在10位元50百萬赫茲管線雙步式類比數位轉換器之高性 能運算放大器和比較器的設計。此運算放大器稱為互補折疊式運算放大器 ，其乃運用一對稱型之互補輸入級和堆疊型之輸出級來提供一較大的單一 增益頻寬及低頻電壓增益，並且因堆疊型之輸出級所以不需米勒補償電容 ，輸出負載及為主極點所在。在負載為1p法拉、消耗功率為35毫瓦特下模 擬結果為：直流增益為66分貝、單一增益頻寬為200百萬赫茲、相位邊際 為40度、安定時間為20n秒。其晶片面積為630微米*370微米。在比較器部 份，我們運用串接二放大器來提高增益，並使用輸入取樣網路及輸入偏移 消除技術來取樣訊號和消除共模雜訊之影響。在消耗功率為1m瓦特下模擬 結果為：自動歸零時間小於10n秒、解析度0.02伏特。晶片面積為364微 米*178微米。 High performance operational amplifier and comparator for use in a 10-bit 50-MHz pipelined two-step A/D converter are introduced in this thesis. This operational amplifier is a complementary folded cascode amplifier which has a larger unity- gain B.W. and low-frequency voltage gain and does not need miller compensation capacitor with symmetrically configured complementary input stage and cascode output stage. The simulation results demonstrate a dc- gain of 66dB approximately, a unity-gain bandwidth of 200MHz, phase margin of 40 degree and settling time of under 20ns with a 1pF load and 35mW power consumption. Layout area is 630um*370um. On the part of comparator, we utilize twocascode amplifier to supply a high gain and make use of both sampling network and input offset cancellation technique to samplimg analog signal and to eliminate the effect of common-mode noise, respectively. The simulation results show that the auto-zero time is below 10ns and resolution is 0.02V(1/4 LSB) with 1mW power dissipation . Layout area is 364um*178um.