交換電流式積分器之設計及其在濾波器設計上之應用

Abstract

交換電流式 (SI) 電路是一種能夠用標準數位式CMOS製程製造類比取樣電 路的一種電路技巧。在所有基本的SI電路中，記憶胞電路是最原始的元件 。這些基本的記憶胞電路能妥善地聯結以建構狀態變數濾波器所用之積分 器和微分器或是在有限脈衝響應 (FIR) 結構中所用之延遲線。因此，SI 系統的類比效能直接受其組成之記憶胞電路的誤差所影響。在這篇論文中 ，首先描述基本記憶胞的基本原理和準確度限制。為增進整體電路的效能 ，我們設計了一個採用負回授電路及突波抑制技巧的記憶胞電路。利用此 記憶胞電路，我們提出一系列的 SI積分器。這些SI積分器經適當的串接 ，加上特定的回授電路後，即構成SI濾波器串級設計所需之通用型一階及 二階建構方塊。這些通用的建構方塊能用來實現所有種類的一階及二階濾 波器。為驗證電路的精確度，我們已經設計了一個一階低通濾波器、一個 二階Chebyshev低通濾波器及一個五階Chebyshev 低通濾波器，並且用 HSPICE做電路的模擬分析。所有模擬的結果與理論值均相當吻合。 The switched-current (SI) circuit is a circuit technique which is able to realize analog sampled-data circuits with a standard CMOS process. Of all the basic SI circuits, the me- mory cell is the most primitive. The basic memory cell can be appropriately connected to construct the integrators and differentiators for state-variable filters and delay lines for finite impulse response (FIR) structure. The analog per- formance arises directly from the errors of its constituent cells. This thesis begins with a description of the element- ary principles and accuracy limitations of the basic memory cell. To enhance circuit performance, the design of a pract- ical memory cell which employs negative feedback and glitch reduction technique is presented. Based on the cell, a fami- ly of SI integrators are then developed. By cascading these integrators with proper feedback, general first and second order sections are developed for cascade design of filters. Test filters have been designed and simulated with HSPICE. Simulated results agree closely with theoretical results.