深次微米SOI MOSFET的設計方法

Abstract

本文利用二維數值分析及解析模式發展一個深次微米SOI MOSFET元件的新 設計方法。為了瞭解短通道SOI MOSFET元件的複雜元件物理，本文利用二 維分析法所推導的臨界電壓模式，來分析元件結構及製程參數對臨界電壓 及洩極感應能障降低的影響。同時，為了區分SOI MOSFET工作於完全空乏 或部份空乏狀況，本文亦發展一個簡單的模式，以協助設計及判斷。另外 ，本文亦利用二維分析法，分析SOI MOSFET元件之電位分佈及次臨界電流 與元件結構及製程參數間的關係，並且區分洩極感應能障降低及抵穿效應 。根據發展完成的SOI MOSFET設計方法，本文設計完成 0.1微米通道長度 的SOI MOSFET，並且展示此元件的優異電流─電壓特性，包括次臨界電流 及導通的電流─電壓特性。 This thesis presents a new design methodology for deep- submicrometer SOI MOSFET's using both 2-D numerical analysis and analytic models. In order to understand the complicate device physics underlying short-channel SOI MOSFET's, a threshold-voltage model based on quasi-2D analysis is used to analyze the effects of device structure and process parameters on the threshold voltage and the drain-induced barrier lowering of short-channel fully-depleted SOI MOSFET's. Moreover, a simple criterion is developed to identify fully- depleted and partially-depleted operations of a SOI MOSFET. In addition, the 2-D numerical analysis is used to verify the structure and process parameters on the potential distribution and the subthreshold I-V characteristics from which the drain- induced barrier lowering and the punch-through effects can be easily identified. Based on the developed new design methodology, a 0.1um channel-length SOI MOSFET is designed and its excellent I- V characteristics including subthreshold and turn-on I-V characteristics are demonstrated.