四運算單元之視訊處理器設計

Abstract

本篇論文提出一具有四個平行管線化運算單元之可程式視訊處理器，我們 稱其為4P-VSP。藉由所設計的資料流架構，所有的運算單元與儲存單元皆 可平行運作，因此非常適合多種視訊演算法之應用。此外，我們亦設計一 些向量指令以支援向量型態(Vector-type)、累加型態(Accumulation -type)、累加及比較並行運作型態(Accumu-lation with MMD-type)等處 理模式以增進運算效率。經由如此設計的向量指令，我們已證實整個運算 能力將因此提昇五倍以上。此視訊處理器已利用TSMC的0.8um CMOS製程來 實現，配合著工研院電通所提供的標準元件庫之時序特性，所有的模組都 用邏輯閘來描述，其功能與時序已用Verilog-XL驗證完成。當系統時脈速 率為36MHz時，最大運算能力為1214-MOPS，最大資料產出(throughput) 為55Mbits/s，適合作即時視訊(MPEG I規格)處理。此4P-VSP晶片之電晶 體總數約為58萬顆，各模組之Layout並已用Cadence軟體完成。 In this thesis, we present a programmable video signal processor which includes four parallel-pipelined processing units, named 4P-VSP. Using the designed datapath architectures, all processing units and storage units can operate concurrently and it is suitable for many video algorithm applications. Moreover, we also designed some vector instructions for the 4P-VSP to support vector- type, accumulation-type and accumulation-with-MMD-type processing modes to increase the execution efficiency in video applications. It has been shown that the performance can be improved more than 5 times via using the designed vector instructions. The 4P-VSP is designed with 0.8um CMOS TSMC'S technology. In consideration of future implementations, gate- level description is adopted in all modules, based on the timing characteristics of CCL08-V1.0 Standard-Cell Library, the 4P-VSP has been verified via Verilog-XL simulation. Under the system clock of 36MHz, the maximum performance is 1214-MOPS and the maximum data throughput rate is about 55M bits/s. The 4P-VSP contains about 580k transistors and the layout of each function block has been done by using Cadence tools.