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dc.contributor.authorKuo, Chien-Ien_US
dc.contributor.authorHsu, Heng-Tungen_US
dc.contributor.authorChang, Chia-Yuanen_US
dc.contributor.authorChang, Edward Yien_US
dc.contributor.authorHsu, Heng-Shouen_US
dc.date.accessioned2014-12-08T15:07:38Z-
dc.date.available2014-12-08T15:07:38Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0636-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/6001-
dc.description.abstract80-nm-gate In(0.7)Ga(0.3)As/InAs/In(0.7)Ga(0.3)As composite channel high-electron mobility transistors (HEMTs) fabricated using platinum (Pt) buried gate as the Schottky contact metal were evaluated for RF and logic application. After gate sinking at the 250 degrees C for 3 minutes, the device exhibited a high g. value of 1590mS/mm at V(d) = 0.5V and the current gain cutoff frequency f(T) was measured to be 494 GHz. The intrinsic gate delay time was calculated to be 0.78 psee at supply voltage of 0.6 V. This is the highest f(T) achieved for 80 nm gate length HEMT devices. These superior performances are attributed to the reduction of distance between. gate and channel, and the reduction of parasitic gate capacitances during gate-sinking process.en_US
dc.language.isoen_USen_US
dc.titleEvaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technologyen_US
dc.typeArticleen_US
dc.identifier.journalEDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGSen_US
dc.citation.spage255en_US
dc.citation.epage258en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000254170700065-
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