完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, C. T. | en_US |
dc.contributor.author | Tsui, Bing-Yue | en_US |
dc.contributor.author | Liu, Hsu-Ju | en_US |
dc.contributor.author | Lin, Geeng-Lih | en_US |
dc.date.accessioned | 2014-12-08T15:07:38Z | - |
dc.date.available | 2014-12-08T15:07:38Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-1-4244-0636-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/6013 | - |
dc.description.abstract | The impact of the high-voltage drift n-well (HVNW) and shallow trench isolation (STI) regions on the electrical characteristics of 32V symmetry and asymmetry n-channel laterally diffused drain MOSFET (N-LDMOS) were evaluated. Asymmetry structure has higher threshold voltage owing to the transient enhancement diffusion (TED) of boron near source region. The smaller extension of the HVNW to STI (E(HVNW-STI) for asymmetry structure exhibits a wider safe-operating-area (SOA) from the hot-carrier reliability point of view. To obtain a higher on-current, the EHVNW-STI should be optimized because the steep sidewall of the STI may force current to flow through a longer distance in the HVNW. Finally, increase of EHVNW-STI cannot efficiently increase breakdown voltage. | en_US |
dc.language.iso | en_US | en_US |
dc.title | The impact of high-voltage drift n-well and shallow trench isolation layouts on electrical characteristics of LDMOSFETs | en_US |
dc.type | Article | en_US |
dc.identifier.journal | EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS | en_US |
dc.citation.spage | 267 | en_US |
dc.citation.epage | 270 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000254170700068 | - |
顯示於類別: | 會議論文 |