IDEA晶片設計

Abstract

隨著電腦網路的普及化，在開放式的網路上傳遞資料的機會與日俱增 。為了保護這些在網路上傳遞的資料之私密性，加密是種可行的方式。但 隨著高速磁碟和網路的發展，這些加密的演算法以軟體方式進行，在速度 上無法滿足一些應用程式在及時( real time ) 上的要求，而以硬體方式 進行已被證實可解決這個問題。在這篇論文中，我們就是描述以超大型積 體電路將IDEA加密演算法做硬體實現的方法。其中IDEA加密演算法是一個 在90年初期提出的新加密演算法，其設計規律適合以硬體實現，且最重要 的是安全性這幾年下來已被廣泛地接受。我們在設計上的特點包括：在 IDEA的每回合(round)中應用了4 個階段(stage)的管線(pipeline)架構。 另外資料加密的動作和輸入、輸出也是以管線的方式執行。此外為了適用 於各種不同的應用和加強保密效果，四種區塊加密的標準模式 ( ECB、 CBC、CFB、OFB)都有支援。預估我們這顆晶片完成後，所有資料的加密和 解密工作均可在單一的硬體單元上完成，並可使用於磁碟與高速網路之及 時加解密應用上。 Due the rapid development of the computer network, there have been more and more chances to transfer information in the open environment. Encryption is a practical method to protect the private secrets in such environment. However, encryption is often a computation-intensive task that can not be effectively performed by microprocessors. Specialized hardware is a solution to this problem. In this thesis, we describe the design of an IDEA chip. IDEA is a new cipher whose regular structure suitable to be implemented in hardware. Most importantly, it has been accepted widely in security. In our design, we adopt a four- stage pipelined architecture for each round of IDEA. The data input, data encryption and data output are also executed in a pipelining fashion. Additionally, for different applications, the four standard operation modes of block ciphers, ECB, CBC, CFB and OFB are supported. It is expected that the design can perform data encryption and data decryption in a single hardware unit after accomplished. The design can be applied to on-line encryp tion in high-speed network and disk applications.