以目錄型態為基礎之快取記憶體一致性多階內聯網路

Abstract

多階內聯網路是眾所皆知, 一種具有高度擴充性及容錯能力之結構, 適合多處理機系統做為其內聯網路之用. 而傳統多階內聯網路的交換器, 因為缺乏一個快速的廣播媒介與維持快取記憶體一致性所需之目錄資料, 未為有效率的支援快取憶體一致性的協定. 在本論文中, 我們嘗試使用將 一群快取記憶體之資訊放置在最低階層的交換器目錄內以達成資料的一致 性. 利用這種目錄的方式, 一個可維持多份快取記憶體資料拷背的協定也 發展出來, 並試著減少每個處理器群之間為資料一致所需之網路交通量. 為此架構, 一個系統效能的分析模型亦被發展出來. Multistage Interconnection Networks (MIN's) are known to be highly scalableand fault tolerent structures for large multi- processor interconnections. Theconventional MIN's switches do not support cache coherence protocols efficiently due to the lacks of a fast broadcasting medium and cache coherentdirectory information. In this paper, we introduce a directory of cache linestate information into the lowest level Min's switches each connects a clusterof processors. A multiple shared cache coherence protocol is developed to usethis directories scheme to reduce the network traffic for cache coherencebetween the clusters of processors. Analytical model for this cache coherentarchitecture is also developed.