適用於深次微米金氧半場效電晶體的低溫製程之研究

Abstract

基體工程(substrate engineering)對於短通道(~ 100nm)金氧半電晶體 抑制短通道效應是極重要的。但是在高溫時，通道的摻雜會因擴散而寬化 ，因此，低熱預算及低溫製程是必需發展的。在本論文□，為了因應通道 非均勻摻雜(ALD,原子層結構)結構之P型金氧半電晶體需要，我們發展了 低溫矽磊晶成長(＜600℃)，低溫選擇性磊晶成長(SEG)，及以低於700℃ 的濕氧化(wet oxidation)成長超薄閘極氧化層等低溫製程模組。磷摻雜 矽磊晶層是以超高真空化學氣相沈積(UHVCVD)系統成長，超高真空化學氣 相沈積法能準確控制雜質分佈。在選擇性磊晶成長方面，我們在乾性蝕刻 之後，藉由低能量電漿處理矽表面以去除污染及缺陷，再作選擇性磊晶成 長，獲得了極佳的矽磊晶層。最後我們以650℃及 700℃濕氧化成長閘極 氧化層並研究其特性，結果證實其應用在ALD金氧半電晶體製造的可行性 。 Substrate engineering of short channel (~100 nm) MOSFETs is critical for suppressing short channel effects, but it suffers from the channel doping profile broadening at high temperature. Therefore, low thermal budget and low temperature process must be developed. In this thesis, low temperature process modules include low temperature Si epitaxy (< 600℃), low temperature selective epitaxial growth(SEG), and a low temperature thin gate oxide grown by wet oxidation on below 700℃ were developed for the demands of the pMOSFETs fabrication with doped channel (ALD, atomic layer doped) structures. Phosphorus-doped Si epilayers were grown by a cold-wall ultra high vacuum chemical vapor deposition(UHVCVD) system. UHVCVD-Si epitaxy technology can precisely control the impurity profiles. Superior SEG layers were achieved by using low energy plasma after-etching- treatment(AET) after the overetching of Si substrates. The characteristics of gate dielectrics grown by low temperature wet oxidation at 650℃and 700℃ respectively are investigated and shows that they are acceptable for fabricating ALD MOSFETs.