應用於非同步傳輸模式交換系統之標頭轉換器的設計與製作

Abstract

鑑於非同步傳輸模式儼然成為寬頻整合服務數位網路的重要技術，本篇論 文擬設計一符合經濟效益的非同步傳輸模式交換系統之標頭轉換器。此標 頭轉換器應用於非同步傳輸模式的交換系統的前端，主要是用來將非同步 傳輸模式的標準晶胞格式及符合交換系統的內部格式做互換。如果遇到 OAM晶胞或是使用者自訂的IMC晶胞，則必須截取此晶胞置於緩衝器中，並 告知微處理器以待進一步的處理。如果沒有資料送入或是送入的資料無法 更新，標頭轉換器必須有所因應。除此之外，標頭轉換器也必須避免輸入 與輸出間資料阻塞，以及傳輸微處理器送出的OAM晶格。 標頭轉換器中最重要的工作就是查表及替換，在諸多查表的方式中，我們 使用位元比較的方式進行查表。這種比較方式是同時取出表中各列的某一 位元來和我們的輸入資料做比較，一次比較各列的一個位元，完全查表所 需的時脈數等於表中任一項資料的位元數；而且無論表有多大，完全查詢 整個表的時間固定不變的。倘若表中某一項資料先送入的資料位元和輸入 資料位元不相等，則這一項資料就絕對和輸入資料不相等，往後的位元也 就不必繼續比較了。利用這一個特性，我們設計一個可以關掉電源的比較 器；如此的設計，的確使得消耗功率節省了(T/(U+M+T))x98.89%，其中M 表示表中和輸入資料位元相對應的位元 總數，而U為表中和輸入資料位元 不對應的位元總數，T則為不比較的位元總數。 配合共享緩衝器( SBF)以及多點傳播伺服器(MCS)，我們得以製作一塊符合經濟效益的非同 步傳輸模式交換系統。這個交換系統擁有32對輸入及輸出，各為155.52 Mb/s。增加每個輸出入的接腳數為4，我們可以降低晶片的處理速率；本 晶片的工作頻率訂於38.88MHz以符 合155.52Mb/s，採用全客戶設計與合 成的方式設計，CMOS SPDM 0.8um製程製作。總電晶 體數為544K，面積 為10137.9 x 8456.4 um2. Since ATM becomes a key technology for B-ISDN, it is necessary to provide a cost-effective VLSI solution for such high-speed digital network. In this thesis, we design and implement a Header Translator (HT) that is the front endcomponent of an asynchronous transfer mode (ATM) switch. It is used to translate an ATM standard cell format into an internal routing cell format, and vice versa. If HT checks an OAM cell or user defined IMC cell exists, it will extract the cell into an OAM buffer and activate a signal to mP. HT willmodify the output if there is no input cell or no matched routing information.It also has to justify the data flow between the input or output terminal and transmit OAM cell from the mP to the output. The major work for HT is to "search" and "replace". Among several searching methods, we choose a Bit Level Comparison (BLC) method which compares the input data with those data stored in a table bit by bit for each entry. The number of clock cycles to finish searching the whole table equals to the bit number of each entry, which keeps constant even the word length of table growslarge. If one bit of some entry does not match with the corresponding input bit pattern, this entry will not be the same with the input pattern and therefore it is not necessary to compare it any more. According this property, a comparator which could be turned off is designed in this thesis. This comparator could save about (T/(U+M+T)) x98.89% for power dissipation, where M is the total bit number of bit cells which matches with the input pattern, U is those which does not match with the input pattern, while T is those with turned off power. Combining with Shared Buffer (SBF) and Multicast Server, we can integrate a cost-effective ATM switch which has 32 input ports and 32 output ports with speed 155.52 Mb/s per port. By increasing pin count as 4 per port, we can lower the operating speed of our chip. In this design, HT chip operates at 38.88MHz and it meets 155.52 Mb/s per port. HT is fabricated in CMOS SPDM 0.8um technology and implemented as a mix of custom and synthesized design approaches. The chip contains 544k transistors within 10137.9 x 8456.4mm2 area.