RSA公開金匙密碼系統處理器之設計

Abstract

隨著電子通訊網路的使用日益增加﹐通訊上的資訊安全和保密也日益重要 。RSA 密碼系統是少數可以達到資訊加密和解密以及數位簽署的公開金匙 系統﹐並且在工業界中已成為被廣泛使用的標準。在RSA密碼系統中需要 對很長的位元序列作餘數的指數運算。而餘數的指數運算可以化簡為一連 串的對餘數的乘法運算。蒙哥馬利的演算法常使用在最近提出的高速RSA 運算方法之中。 但這些方法最後結果產生之前﹐會有餘數過大的情形﹐ 而需要多餘的減法﹔或者是需要將冗餘的中間值轉化成一般的位元表示法 。在這篇論文中我們修改蒙哥馬利的演算法來避免這些多餘的運算﹐並且 減短餘數的乘法運算中﹐最關鍵的時間延遲。根據我們修改過的演算法﹐ 我們採用Compass 0.6um SPDM 細胞庫來實作一顆512-bit 的 RSA 處理器 。以我們修改的餘數指數演算法﹐一個n-bit的餘數指數運算在我們的硬 體架構中大約需要1.5n*n 的時脈。在125Mhz 的時脈下﹐我們的晶片可以 達到164k bits/sec的鮑率。我們的晶片邏輯閘數目總共是74k﹐晶片大小 是7996.8mm x 6993.9mm。 With the growing use of telecommunications networks, the communication security becomes more and more important. RSA cryptosystem is the most versatile and most widely used public key cryptosystem today. RSA cryptosystem involves modular exponentiation operations on extremely long bit streams. Modular exponentiation can be performed by successive modular multiplications. Recently proposed methods for faster implementation of RSA cryptosystem were based on the Montgomery' s modular multiplication algorithm. Most of these methods suffered from the over-large residue or converting the redundant intermediate results into non-redundant binary representation. In this thesis, we proposed a modified algorithm to avoid these problems and reduced the hardware depth for performing the modular multiplication steps. We have implemented a 512-bit single chip RSA processor based on our modified algorithm with Compass 0.6mm SPDM cell library. By our modified modular exponentiation algorithm, it takes about 1.5n*n clock cycles to finish one n-bit modular exponentiation operation in our architecture. The baud rate of the processor is about 164k bits/ sec at 125Mhz clock frequency. The gate count of our chip is about 74k, and the die size is about 7996.8um x 6993.9um.