閘控雙載子電晶體之新穎應用:動態臨界電壓互補式金氧半電路及簡潔的靜態隨機存取記憶體單元

Abstract

本論文探討兩個以 0.5 微米互補式金氧半製程實現的閘控側向雙載子電 晶體的新穎應用。一個為電容耦合動態臨界電壓互補式金氧半數位電路； 另一個為簡潔的靜態隨機存取記憶體單元。前者為動態臨界電壓的反相器 及由其構成的漣波振盪器，當在主動操作時藉由閘控側向雙載子電晶體的 動作而使臨界電壓降低；後者為簡潔的靜態隨機存取記憶體單元，其僅由 一個 n-p-n 高增益閘控側向雙載子電晶體和一個 p 型金氧半電晶體組 成。暫態的量測結果顯示，當電源電壓由 1.5 伏特降至 0.8 伏特，因由 於閘控側向雙載子電晶體的動作而使得反相器的延遲時間改善了約十倍， 而漣波振盪器的振盪頻率會隨著不同電源電壓下反相器的延遲時間改變而 改變。另外，我們對新式簡潔的靜態隨機存取記憶體進行讀寫量測，證明 其確實存在高與低兩個邏輯穩態。此記憶體單元乃是基於閘控側向雙載子 電晶體的基極電流逆轉特性。其優點有：只需單側的周邊電路即可進行讀 寫、節省晶片的面積以及完全相容於現今的低成本、高良率、穩定的互補 式金氧半製程。 This thesis explores two novel gated BJT applications realized in a 0.5 um CMOS process: the capacitively-coupled dynamic threshold CMOS digital circuit and the compact SRAM cell. The former is presented in terms of an inverter and a ring oscillator both with the threshold voltage magnitude lowered via gated lateral bipolar action during the active switching. The latter comprises a total of only two MOSFETs, an n-MOSFET and a p-MOSFET. In this compact cell the n-MOSFET is operated as a three-terminal high gain gated lateral bipolar transistor. Extensive transient measurement experiment exhibits that as the supply voltage is reduced from 1.5 V to 0.8 V, the delay time in the inverter can be improved by about 10 times if the gated BJT action is implemented. The measured oscillating frequency from the ring oscillator having the gated BJT action has been found to follow the measured delay time of the inverter as the supply voltage is changed. On the other hand, our compact SRAM cell has successfully provided two stable states for high- and low-level logic, as has been demonstrated experimentally by the Read/Write characterization. This feature is due to base current reversal in gated BJT. The compact SRAM cell can also offer advantages: only one-sided peripheral circuitry for Read/Write function, small chip area consumption, and full compatibility with existing low cost, high yield, stable CMOS processes.