雙模式 IS-54 Viterbi 解碼器設計

Abstract

在二十一世紀初，無線電話將大量增加，約有一半的人口需要此 服務。可是現有的類比系統，無法滿足此服務需求，因此推出分時多工存 取(TDMA)數位系統取代傳統的類比系統。本篇論文提供IS-54的解碼器設 計，根據IS-54的標準，將每個使用者每秒可傳輸的16200 bits 的資料量 分成語音-每秒7950 bits，語音保護-每秒5050 bits，SACCH-每秒600 bits和其它-每秒2600 bits。設計重點包括：可開關的(2,1,5)及(4,1,5) 解碼器設計，資料的交錯(interleaving)，軟式決定(softdecision)。因 為硬體的限制，手機的設計必需考慮面積的有效運用，因此，最佳化的面 積的有效運用將施行。此編碼器的速度是每秒1.57百萬位元，符合IS-54 中語音保護碼解碼的要求，此晶片的大小為3.96 mm * 3.58 mm。此交錯 器(Interleaver)的速度是每秒50百萬位元，晶片大小為4.89 mm * 4.20 mm。 The market for cellular telephony is expected to increase dramaticallyduring the 2000's. Service may be exceeded 50% of the population. This is beyond the ranges with the present generation analog cellular systems. The time division multiple access (TDMA) digital system is instead of conventional analog cellular system.In the thesis, we provide a VLSI design of Viterbi decoder for IS-54.In IS-54 standard, the 16.2 kb/s per user are divided into speech codec 7.95 kb/s, error protection of speech 5.05 kb/s, SACCH 0.6 kb/s, guard time, sync, color code, ramp up 2.6 kb/s, Design features include : switchable ( 2, 1, 5 ), ( 4, 1, 5 ) coder design, data interleaving, soft decision. For hardware constrain, area efficiency is of great concern in handset design. Hence, optimized area efficient design is implemented. The decoding rateis 1.57 MHz, it is suitable to IS-54 for error protection of speech. The core size is 3.96 mm * 3.58 mm. The clock cycle of interleaver is 50 MHz and core size is 4.89 mm * 4.20 mm.