採用八位元280MS/s多重取樣單轉換CMOS類比數位轉換器的正交解調器

Abstract

在本篇論文裡提出一個操作於70百萬赫互補式金氧半中頻正交解調器積 體電路.此解調器使用了一個操作於四倍中頻,即280百萬赫的取樣保持電 路.中頻調變訊號被連續取樣至I及Q頻道的取樣電容陣列中(取樣電容陣列 中的電容比值代表了I及Q頻道濾波器的係數),透過取樣電容中電荷相加的 方式完成濾波的功能,濾波後的離散基頻訊號再經八位元連續漸進式類比 數位轉換器予以數位化輸出.每個頻道的輸出速率為1.09MS/s.此使用多重 取樣,單轉換架構且包含降頻混波器,低通濾波器,連續漸近式類比數位轉 換器的中頻正交解調器已透過0.8um DPDM製程予以實現.晶片尺寸為5000 x4000微米平方,平均消耗功率為100毫瓦. In this thesis, a CMOS 70 MHz IF Quadrature demodulator is presented. This IFdemodulator uses the sample-and-hold ckt operated at 4 times IF frequency,280MHz The IF modulated signal is sampled successively to different capacitors in samplingcapacitor array of I and Q channel(The capacitor ratios in sampling capacitor arrayrepresent the coefficient of IQ channel filter).The filter function is achievedby analog charge addition in sampling capacitors.The resultant discrete-time basebandI and Q signals are digitalized by 8-bit successive approximation ADC.The dataoutput rate in each channel is 1.09MS/ s. This IF quadrature demodulator which includes mixer,lowpass filters and successiveapproximation AD converter and utilizes the multiple sampling,single conversionarchitecture is fabricated in UMC 0.8 DPDM CMOS process.The whole chip area is5000um x 4000um,and the average power dissipation is about 100mW.