三度空間電腦繪圖處理器之後級設計

Abstract

本論文研究三度空間電腦繪圖的運算，並從既有的架構中實現三度空 間電腦繪圖處理器的後級，其中包含 frame buffer 中與 stencil buffer、Z 及 RGBA buffer 相關的運算單元。文中分析一般常用的記憶 體晶片，並選擇 BEDO DRAM 和 VRAM 作為 frame buffer 的儲存元件。 最後採用 PHILIPS 3.3 伏特 0.5微米三層金屬製程的 cell library， 以 Synopsys 合成 Verilog HDL 程式實現硬體設計。模擬結果中 local buffer 的最高效率為 20M pixels/sec，RGBA buffer 為 5M pixels/sec 。 In the thesis, post-processing of 3D Graphic Rendering Processor (3DGP) is studied. A proposed architecture for 3DGP is implemented, which includes the operations related to stencil, Z and RGBA buffers. The charcateristics of various RAM (Random Access Memory) chips are analyzed, then BEDO DRAM and VRAM are choosen for frame buffer storage. Finally, the designs written in Verilog HDL are synthesized by Synopsys using PHILIPS' cell library which is based on 3.3V, 0.5um, triple-metal semiconductor technology.The results of simulation show that the peak performance of local buffer is 20M pixels/sec, and RGBA buffer is 5M pixels/sec.