Title: 應用於準收縮陣列架構之半點精確度全搜索動態影像預估
A Half-Pixel Precision Full-Search Motion Estimation Processor Based on Semi-Systolic Array Architecture
Authors: 黃宏仁
Huang, Hong-Zen
李鎮宜
Chen-Yi Lee
電子研究所
Keywords: 準收縮陣列;半點精確度;動態預估;semi-systolic array;half-pixel precision;motion estimation
Issue Date: 1995
Abstract: 本論文提出一顆基於全搜尋方塊比對演算法,並且可以達到半點精確
度之動態影像預估處理器,此外,能夠符合 MPEG-2 標準之不同預估模式也
是本架構的特色之一,而提出的電路架構是由半心縮陣列(semi-systolic
array)架構所衍生而來,此架構在運算之中能夠達到100%的硬體使用效率
。整體架構分配考量之下,整個電路可以分為三大部份,分別為整數圖素處
理單元(IU)、新式的半點圖素處理單元(HU),以及中央控制單元,而在各個
部份之間有著些許微妙的關係存在於彼此之間。本論文同時也提出一個新
式資料共享方式,使的 HU 在運算中所需要的所有資料都可以由內部的記
憶體提供,而不需要由外界來供應,如此可以大幅的降低 I/O bandwidth
,也提昇了硬體使用效率,此外,為了使本架構可以充分應用於 MPEG
encoder 之中,本架構在設計時也一併考慮到與其他外界電路作配合,諸
如:與 MMU 之間做資料傳輸商議。在 TSMC SPDM 0.8um 製成技術下,此架
構共用492K 電晶體,晶片大小為 13.39mm x 6.13mm,而模擬結果顯示本晶
片時脈速度可以達到100Mhz,這意味了本架構不但可以應用於 MPEG-2 標
準,而且也可以達到即時處理編碼的要求。
In this thesis, a VLSI architecture of a half-pixel precision
full-search motion estimation (ME) processor is proposed for
evaluating both integer and half-pixel motion vectors. Besides
half-pixel precision, correspondence with four prediction modes
on MPEG-2 standard is also a key feature on the
proposedarchitecture. The proposed architecture is based on
semi-systolic array ME architecture which can achieve 100%
hardware efficiency in processing element (PE) array. The
floorplan roughly divides overall architecture into three
majority parts, namely integer unit (IU), half-pixel unit (HU)
and central control unit, and some ingenious relations exist
among them onto the data flowschedule. IU mainly consists of
four units, namely memory bank unit, 2-D PE array, summation
unit, and comparison unit. In turn, HU chiefly comprises
fivecomponents, called memory unit, interpolation unit, 1-D PE
array, comparison unit, and motion vector generator. Control
unit is reponsible for giving accurate control of four
prediction modes. We pay emphasis on the performance in HU which
not only dramarically reduces the I/O bandwidth of the off-chip
memory but also generates more precise motion vector for
supporting MPEG-2 standard. Based on TSMC SPDM 0.8um process
technology, it integrates about 492K transistors in a 13.39mm
x 6.13mm silicon die. Simulation results show that clock speed
up to 100Mhz can be achieved, implying that the proposed
architecture can meet the real-time requirement of MPEG-2 MP@ML.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT840430070
http://hdl.handle.net/11536/60674
Appears in Collections:Thesis