應用於MPEG2視訊壓縮之高效益記憶體管理之設計與製作

Abstract

本篇論文提出一個應用於MPEG2 MP@ML編碼器與解碼器的記憶體管理 支超大型積體電路架構。解碼器架構為一可程式化的設計以提供系統控制 器一個更具彈性的記憶體管理。我們較著眼於編碼器記憶體管理設計使其 除了提供ME，DCT/IDCT及外部記憶體間資料流向控制外還具有macroblock type的選擇能力。此功能將影響到壓縮後影像品質及編碼後bitstream長 度。在設計編碼器記憶體管理單元時我們以節省面積減少功率消耗以及模 組化設計為主。並提供一個同步動態隨機存取記憶體介面。由模擬結果顯 示，我們的設計可達50MHz可應用於MPEG2 MP@ML 及時影像壓縮。 In this thesis, VLSI architectures are proposed for encoder and decodermemory management design targeted to real-time MPEG2 MP@ML. The architectureof decoder is a programmable design which provides more flexibility to system controller in the memory control. We pay more emphasis on the designof the encoder memory management which supports not only the manipulationof data flow between ME, DCT/IDCT and external memory, but also the abilityof macroblock type selection which is related to the compressed video qualityand coded bitstream length. In theis design, we mainly analyze the data flow in the encoder and find the better timing schdule to reduce the area cost. Weprovide a synchronous DRAM interface in this design for the demands on the video memory in terms of memory capacity and data rate. Power consumption isreduced by the decrease of transition frequency frequency in this design. All functional blocks are designed as modules to simplify the modification in thefuture. Simulation results show that clock speed up to 50MHz can be achieved, implying that the proposed architecture can meet the real-time requirement of MPEG2 MP@ML and provide the suitable macroblock type to VLC.