标题: 应用于MPEG2视讯压缩之高效益记忆体管理之设计与制作
Design and Implementation of Cost Effective Memory Management for MPEG2 Video Compression
作者: 张荣哲
Chang, Long-Jer
李镇宜
Lee Chen-Yi
电子研究所
关键字: 记忆体管理单元;memory management unit
公开日期: 1995
摘要: 本篇论文提出一个应用于MPEG2 MP@ML编码器与解码器的记忆体管理
支超大型积体电路架构。解码器架构为一可程式化的设计以提供系统控制
器一个更具弹性的记忆体管理。我们较着眼于编码器记忆体管理设计使其
除了提供ME,DCT/IDCT及外部记忆体间资料流向控制外还具有macroblock
type的选择能力。此功能将影响到压缩后影像品质及编码后bitstream长
度。在设计编码器记忆体管理单元时我们以节省面积减少功率消耗以及模
组化设计为主。并提供一个同步动态随机存取记忆体介面。由模拟结果显
示,我们的设计可达50MHz可应用于MPEG2 MP@ML 及时影像压缩。
In this thesis, VLSI architectures are proposed for encoder
and decodermemory management design targeted to real-time MPEG2
MP@ML. The architectureof decoder is a programmable design which
provides more flexibility to system controller in the memory
control. We pay more emphasis on the designof the encoder memory
management which supports not only the manipulationof data flow
between ME, DCT/IDCT and external memory, but also the abilityof
macroblock type selection which is related to the compressed
video qualityand coded bitstream length. In theis design, we
mainly analyze the data flow in the encoder and find the better
timing schdule to reduce the area cost. Weprovide a synchronous
DRAM interface in this design for the demands on the video
memory in terms of memory capacity and data rate. Power
consumption isreduced by the decrease of transition frequency
frequency in this design. All functional blocks are designed as
modules to simplify the modification in thefuture. Simulation
results show that clock speed up to 50MHz can be achieved,
implying that the proposed architecture can meet the real-time
requirement of MPEG2 MP@ML and provide the suitable macroblock
type to VLC.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT840430071
http://hdl.handle.net/11536/60675
显示于类别:Thesis