完整後設資料紀錄
DC 欄位語言
dc.contributor.author張宏德en_US
dc.contributor.authorChang, Horng-Deren_US
dc.contributor.author吳介琮en_US
dc.contributor.authorJieh-Tsorng Wuen_US
dc.date.accessioned2014-12-12T02:15:37Z-
dc.date.available2014-12-12T02:15:37Z-
dc.date.issued1995en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT840430085en_US
dc.identifier.urihttp://hdl.handle.net/11536/60690-
dc.description.abstract本篇的論文描述一個工作在 2 伏, 110 MHz 的相位及振幅的向量調變器 設計.它包含了多相位壓控振盪器, 相位選擇器, 和一個可調增益的輸出 級電路.多向位壓控振盪器是向量調變器的主要核心, 它是 8 乘 4 的陣 列式偶合環圈振盪器,可產生 64 個不同相位的差動訊號. 相位的精確度 可以達到 1/8 個反向器之延遲.使用了三對輸入的反向器細胞元, 保證只 振盪在單一模式下.相位選擇器選出 64 個訊號中的一組訊號送到輸出級 電路. 訊號的選取由一個 6 位元數位輸入的相位解碼器執行. 輸出級是 一個電流模式的電路, 電流增益為 6.輸出級電路也包含了電流分割器, 它把放大的電流等分成 7 等分, 而且由一個 3 位元數位輸入的振幅解碼 器控制.本向量調變器的製程為 TSMC 0.6um SPDM CMOS 的製程, 晶片大 小為2800um x 2800umm, 包含 PAD. 工作電壓為 2 伏, 輸出的中心頻率 為 20 MHz 到160 MHz, 晶片的全耗功率為 80 mW.本向量調變器還包含了 一個相鎖迴路, 由另外一位同學所設計. This thesis describs the design of a 2V, 110MHz CMOS phase- magnitudevector modulator chip, which consists of a multi-phase voltage-controlledoscillator (VCO), a phase selector, and a variable gain output buffer.The multi-phase VCO is the core of the vector modulator. It is a 8 by 4coupled ring oscillator array and can generate 64 differential signals ofdifferent phases. The phase difference is only 1/8 of the gate delay.The use of 3-input delay cell ensures the single operation mode.The phase selectors choose one of the 64 signals for output. The phase is digitally selected by a 6-bit digital input through a phase decoder.The output buffer is a current-mode circuit, which has a current gain of6. A current divider is also included in the output buffer, which has adivide ratio of 1 to 7, and can be digitally controlled by a 3-bit magnitude decoder.The vector modulator has been implemented with the TSMC 0.6um SPDM CMOStechnology. Total chip size is 2800um x 2800um, including pads. Operatingfrom a single 2V supply, the output frequency can vary from 20 MHz to160 MHz. Total power consumption is 80 mW.The chip also includes a phase-locked loop (PLL), which is describes inanother thesis.zh_TW
dc.language.isozh_TWen_US
dc.subject低電壓zh_TW
dc.subject向量zh_TW
dc.subject調變器zh_TW
dc.subjectLow Voltageen_US
dc.subjectVectoren_US
dc.subjectModulatoren_US
dc.title2 伏 110MHz 的 CMOS 向量調變器zh_TW
dc.titleA 2V 110MHz CMOS Vector Modulatoren_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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