一個 2 伏 110 MHz 之 CMOS FM 解調器

Abstract

本篇論文是在描述一個 2V 110 MHz 的 CMOS FM 解調器. 它是利用二 階 Sigma-Delta 超倍數取樣之類比/數位轉換技術來取出外界輸入的載波 訊中的相位訊息. 這個解調器電路使用了一個 4 乘 8 之陣列式環圈振 盪器來鎖住外界參考訊號, 而產生 64 個 110 MHz 之參考相位. 6 個位 元的上數/下數計數器選擇了振盪器所產生的其中一個相位, 而相位/頻率 偵測器用來比較所選出的相位以及輸入訊號的相位之間的差別. 接著相 位/頻率偵測器輸出的相位差訊號經過電荷充放電路後由比較器所量化. 6 個位元的上數/下數計數器則是依據比較器的比較結果來決定其輸出值. 此數位輸出訊號同時也包含了外界輸入訊號的相位訊息. 在這裡差動電 流模式邏輯電路大量的運用在解調器的電路中, 為了就是要減少雜訊所產 生的干擾, 而新式的相位/頻率偵測器及電荷充放電路則使得相位的偵測 更為準確. 此 FM 解調器系統是使用 TSMC 0.6um SPDM CMOS 製程. 工作 電壓為 2 V, 系統的功率耗損為 54mW. This thesis described the design of a 2 V 110 MHz CMOS FM demodulator, which employs a second-order Sigma-Delta oversampling analog-to-digital conversion technique to extract phase informationcarried in the input signal. The circuit uses a 4 array ring oscillator phase-locked to an external reference to generate 64 reference phases at 110 MHz. A 6-bit up-down counter selects one phase from the oscillator, anda phase- frequency detector (PFD) is used to compared the selected phase with the phase of the input signal. The phase difference output from the PFD is filtered by a charge pump circuit (CP) andquantized by a comparator. The 6-bit up-down counter is updated according to the comparison result. The digital output of the comparator also contains the phase information of the input signal. The differential current-mode logic is used for most of the circuit to minimize noise degradation. The new PFD and CP circuits are used to improve phase accuracy. This entire demodulator hasbeen implemented using the TSMC 0.6um SPDM CMOS technology. The chip can operate under a single 2 V supply, and consumes 54mW of power.