標題: 複晶矽薄膜電晶體低溫關鍵製程技術研究
Investigation of Low-Temperature Key Process Technologies for Poly-Si Thin Film Transistors
作者: 林明田
Lin, Ming-Tyan
葉清發
Ching-Fa Yeh
電子研究所
關鍵字: 複晶矽薄膜電晶體;離子披覆;氧離子電漿;耐壓結構;液相沉積;Poly-Si Thin Film Transistor;Ion Plating;Oxygen Plasma;breakdown tolerant structure;Liquid Phase Deposition
公開日期: 1995
摘要: 利用複晶矽薄膜電晶體同時將畫素電晶體以及週邊驅動電路積體化於大 面積玻璃基座已是平面液晶顯示器的重要技術之一,而低溫研製複晶矽薄 膜電晶體將是未來技術的主流.本研究群首度嘗試將離子披覆二氧化矽的 技術應用於複晶矽薄膜電晶體的覆蓋層,並發現藉由此一製程技術,可有效 的降低複晶矽薄膜中的deep state和tail state的密度,進而提高了複晶 矽薄膜電晶體的操作特性.此外,我們利用液相沈積二氧化矽 在適當的沈 積條件下,對光阻據有選擇性沈積的特質,發展初一種新結構的薄膜電晶 體,此新結構的薄膜電晶體可有效降低在主動區邊緣處的閘及氧化層中的 電場強度,進而降低了電晶體的閘極漏電,並加大了電晶體的崩潰電壓. Active-matrix liquid-crystal (AMLCDs) with on-glass peripheral circuit made from poly-si TFTs are one of the most promising technologies for Full-colorfla-panel display. In this reach, low-temperature processed poly-Si thin film transistors have been successfully fabricated by using ion plating(IP)oxide as capping layer. The IP capping technique can dramaticlly reduced the deep-state and tail-state densities and result in an improved performance. Beside, we also propose a novel TFT structure which can reduce the electric field intensity of the gate insulator at the edge of active island by selectively depositing liquid-phase-deposition oxide around the active island to make the pattern globally planarized. The novel structure TFT can successfully reduce the gate leakage current and increase the breakdown voltage.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT840430090
http://hdl.handle.net/11536/60696
Appears in Collections:Thesis