新的可校正電流型 D/A : 系統分析與架構設計

Abstract

本論文提出一種基於二進位權值電流源(Binary-Weighted Current Sources)的可校正式電流型數位類比轉換器(Digital to Analog Converter)架構，藉著一種新的、靜態的自我校正技術來達到其高解析度 ，並且，由於使用二進位權值電流源，而不需要複雜的解碼電路，高速響 應是可預期的。在校正電路中，引入 R-2R 梯階網路，使元件個數大為降 低，為了保證在校正周期的最後能夠達到預期的解析度，我們提出了一種 多段校正的設計準則來作為校正電路設計的依循。文中並提出了一種具有 Window 功能的快速、高解析度電流比較器，來達到高解析度的自我校正 ，藉著對現有的一種電流比較器作偏移量的補償，在 100 nA 的輸入電 流下，可達到大約 45 倍的速度改善，當輸入電流更小時，速度的改善將 更為顯著。漏電的效應也被提出來討論，並藉著漏電路徑的阻斷，由模擬 分析的結果知道︰對於現有的電流比較器而言，解析度由 230 nA 進步到 750 pA，而對於所提出的電流比較器而言，解析度可優於 1 pA。 An architecture of a calibrated-current-type DAC based upon binary-weighted current sources is presented which uses a new self-calibration technique to achieve high resolution. Based upon binary-weighted current sources,complicated decoding of the digital input data is not needed. So it is expected to have a higher speed response. An R-2R ladder network is introduced to minimized the amount of components in the calibrated circuit. And the design criteria for the self-calibration network is proposed to guarantee meeting the desired resolution at the end of the calibration processes. The error introduced by the current amplifier is also discussed and then we know that how accurate is the window current comparator needed. A high speed, high resolution current comparator with function of window detection is developed to achieve high resolution self- calibration. By applying the offset compensation technique to Traff's current comparator, a speed improvement of about 45 times under 100 nA input is achieved. It will have a more significant speed improvement at lower input current levels. The leakage current effect is discussed and an existed technique is introduced to block out the path of the leakage current. The resolution is improved from 230 nA to 750 pA for Traff's current comparator and a resolution better than 1 pA is achieved for the proposed current comparator.