供8-VSB及64-QAM數位信號時脈再生之電路設計與實作

Abstract

本篇論文提出一個供8-VSB及64-QAM數位信號時脈再生之方法。我們希 望經過時脈再生後所得之時脈訊號有精準的頻率。模擬顯示我們的時脈再 生方法能達到此要求。此時 脈再生線路將收到的資料訊號直接處理不需 要在傳輸端加入額外preamble的或是時脈訊號。此時脈再生電路將在機頻 運作，而為避免與載波之間相互影響，我們也將原來線路做些修改。 In this thesis, a timing recovery method is proposed for 8-VSB and 64-QAM digital signals. We desire the recovered timing for the receiver operationhave an accurate frequency. The simulation results show that the requirementis achieved. The timing recovery circuit processes the data signal itself, noadditional preamble or discrete tone is required. We will operate the timingrecovery in the baseband and some modification prevents the interaction withcarrier recovery is also proposed. We implement the proposed timing recoverycircuit in discrete components and construct a filter and some control circuitin FPGA.