Full metadata record
DC FieldValueLanguage
dc.contributor.author陳慈丰en_US
dc.contributor.authorChen, Tzu Fengen_US
dc.contributor.author尉應時en_US
dc.contributor.authorWinston I. Wayen_US
dc.date.accessioned2014-12-12T02:15:44Z-
dc.date.available2014-12-12T02:15:44Z-
dc.date.issued1995en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT840435039en_US
dc.identifier.urihttp://hdl.handle.net/11536/60793-
dc.description.abstract在本論文中, 我們提出一種可使用在數位64 QAM及8 VSB解調器中的載 波再生架構,完成其數學與效能分析,對於不同通道模型與訊號雜訊比作詳 盡的模擬和討論,並且自製出一套數位化載波再生電路來驗證其可行性與 效能. In this thesis, we propose an architecture for carrier recovery in both64 QAM and 8 VSB Modems. We have complete mathematical analysis and performanceevaluation. Also, we simulate and discuss our archiecture in different channelmodels and signal-to-noise ratios. And a digitized carrier-recovery circuit isimplemented to prove the feasibility of our architecture.zh_TW
dc.language.isozh_TWen_US
dc.subject載波再生zh_TW
dc.subject鎖相迴路zh_TW
dc.subjectCarrier Recoveryen_US
dc.subjectCostas Loopen_US
dc.subject64 QAM or 8 VSBen_US
dc.title供數位 64-QAM 及 8-VSB 載波再生電路設計與實作zh_TW
dc.titleCarrier Recovery Circuit Design and Implementation for Digital 64-QAM and 8-VSB Signalsen_US
dc.typeThesisen_US
dc.contributor.department電信工程研究所zh_TW
Appears in Collections:Thesis