供數位 64-QAM 及 8-VSB 載波再生電路設計與實作

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	陳慈丰	en_US
dc.contributor.author	Chen, Tzu Feng	en_US
dc.contributor.author	尉應時	en_US
dc.contributor.author	Winston I. Way	en_US
dc.date.accessioned	2014-12-12T02:15:44Z	-
dc.date.available	2014-12-12T02:15:44Z	-
dc.date.issued	1995	en_US
dc.identifier.uri	http://140.113.39.130/cdrfb3/record/nctu/#NT840435039	en_US
dc.identifier.uri	http://hdl.handle.net/11536/60793	-
dc.description.abstract	在本論文中, 我們提出一種可使用在數位64 QAM及8 VSB解調器中的載波再生架構,完成其數學與效能分析,對於不同通道模型與訊號雜訊比作詳盡的模擬和討論,並且自製出一套數位化載波再生電路來驗證其可行性與效能. In this thesis, we propose an architecture for carrier recovery in both64 QAM and 8 VSB Modems. We have complete mathematical analysis and performanceevaluation. Also, we simulate and discuss our archiecture in different channelmodels and signal-to-noise ratios. And a digitized carrier-recovery circuit isimplemented to prove the feasibility of our architecture.	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	載波再生	zh_TW
dc.subject	鎖相迴路	zh_TW
dc.subject	Carrier Recovery	en_US
dc.subject	Costas Loop	en_US
dc.subject	64 QAM or 8 VSB	en_US
dc.title	供數位 64-QAM 及 8-VSB 載波再生電路設計與實作	zh_TW
dc.title	Carrier Recovery Circuit Design and Implementation for Digital 64-QAM and 8-VSB Signals	en_US
dc.type	Thesis	en_US
dc.contributor.department	電信工程研究所	zh_TW
顯示於類別：	畢業論文