Modulo 2^n+1 乘法器的製作

Abstract

在這篇論文中，我們將以0.6um full custom的方式製作一個高速 modulo乘法器。 這個乘法器採用一個高效率的CSA陣列架構，符合規律 化、模組化與局部化的特性，適 合VLSI的製作。這個架構以正常二進制 （standard binary representation）表示，不 需要碼轉換過程，即可 將處理的部份乘積由(n+1)x(n+1)個降至nxn個，而且這個架構將 部份乘 積位元的weight限制在以2^n下，使得最後總和加總階段只需要簡單的修 正電路。我們在製作過程中特別注意了三點；（1）所使用加法器的進位 與和輸出訊號延遲應力求平衡，（2）乘數與被乘數輸入訊號線的高負載 問題，（3）在最後總和加總階段，如何 選擇一個最適當的進位傳遞（ carry-propagate）加法器。最後經過比較，我們製作的 modulo乘法器 ，無論在面積成本與速度上都較其他做法為優。 In this thesis, we adopt an efficient design and use the TSMC 0.6 um SPDM technology file to implement a modulo 2^n+1 multiplier. This design does not use a special binary representation of numbers in R(2^n+1); however, its hardware complexity is reduced by transforming the number of partial products from (n+1)(n+1) to nxn. Since no code translations is needed, there are very small hardware overheads. This design is well-suited to full-custom implementation since it exhibits a very regular CSA structure composed almost exclusively of full and half adders. In order to construct a high-speed multiplier based on CSA array, we must consider three problems: (1) the delay balance between the sum and carry signals of the full adders, (2) the heavy loading effect of the multiplicand and multiplier signals, (3) the proper carry-propagation adder for the final addition adder. We will present our solutions for the above three problems in this thesis. Finally, the complete layout of modulo 2^16+1 multiplier will be presented.