BESOI的製作

Abstract

由於無線電通訊和超大型積體電路的應用，近年來相關的高速元件和IC 引起了相當的關注。而SOI正能符合上述的需求， 不僅如此， SOI對於IC 的製造也有多項優點﹐例如﹕製程簡化､封裝密度的提高､以及抗高幅射 等等優點。 本論文主要是針對我們新發展的BESOI 製程技術做一探討， 它主要的困難是在於達到低濃度的硼含量，而這亦是低功率和高速元件所 要求的。對於BESOI 的主要高溫製程步驟我們都改以較低溫度來製程，預 期能達到最低硼殘留含量的要求。 我們採用較低溫的800℃ 來做磊晶， 而晶片結合也改用較低溫的600℃ 來完成。而在小心的處理之下的確能大 大的增強晶片的結合力量，它可以媲美傳統用極高溫1100℃來做晶片結合 的效果。 The focus of this thesis is on our newly developed bond and etch-back silicon-on-insulator (BESOI) process. BESOI uses sub- micron epitaxial silicon layers on heavily B-doped Si substrates and subsequently bonded onto another Si wafer with a thermally grown oxide. An etch-back process is followed to remove the Si substrate and the B-doped p+ layer. It is difficult to achieve a fully depleted MOSFET by conventional process with lower B concentration, however it is essential for the low power and highspeed operation. We have used low temperature process on Si epitaxy and wafer bonding. Abrupt B profiles with concentration reduced by three orders of magnitude within hundreds of angstrom is achieved for the Si epitaxial layer at a low growth temeprature of 800℃. A low bonding temeprature of 600℃ with well treated SiO2 surface is obtained to achieve a high wafer bonding energy, which can compete with the conventional high temperature wafer bonding at 1100℃. Todate, the process temperature of our BESOI is still the lowest one.