應用於三維電腦圖學中具有透視效果之紋理貼圖單元之設計

Abstract

三度空間電腦繪圖在現今多媒體和虛擬實境的應用上，已變得愈來愈 重要。在這個領域中，紋理貼圖(Texture Mapping)是一項極為成功的繪 圖技巧之一。它可以使物體或景物看起來更加的真實和複雜。 在 本篇論文中，我們提出了一個新的架構，它可以用來處理具有透視效果的 紋理貼圖以增進電腦繪圖的速度。本顆紋理貼圖器包含了描繪單元( Rasterization)和消除鋸齒單元(Anti-aliasing)。它的特色有: 四邊形 的描繪器，一個在對數域中運算的除法器，和用在消除鋸齒單元的簡化演 算架構。為了提高繪圖的速度和吞吐量(Throughput)，我們採用完全管線 化的設計(Pipeline)。藉由資料流向和運算式的分析，許多資源共享的技 巧可用來降低硬體成本。 根據佈局完成後的模擬結果，系統的 時脈可達71MHz。也就是像素產生的速率是每秒17.85百萬個，10 * 10大 小，具深度值的四邊形產生速率是每秒158.67千個。 本顆處理器有 大約三萬個邏輯閘(Gate)，晶片大小為7522mm*6107mm。整顆晶片都是由 COMPASS 0.6mm HP CMOS的細胞庫(Cell Library)來設計實現的。目前這 顆晶片正由國科會晶片設計製作中心製造。 3D computer graphics has becoming more and more important in modern multimedia and virtual reality systems. In this area, texture mapping is one of the most successful techniques which can make images look more realistic and complex. In this thesis, a perspective texture mapping processor (PTMP) is designed and implemented to improve the texture mapping performance of computer graphics. The PTMP can give the proper effort of foreshortening on texture mapped polygon. The hardware of rasterization and anti-aliasing is incorporated into PTMP.The features of this design include modified four sided polygon scan-converter, logarithm space divider, and simplified algorithms for anti-aliasing. To enhance rendering speed and throughput, the fully pipelined architecture is designed. By analyzing data flows and operations, many resource sharing techniques can be utilized to reducehardware cost. The post layout simulation results show that the system can operate up to 71MHz. That is, the pixel rate is 17.85M pixels per second and 158.67K 10 * 10, Z buffered, polygon rate per second can be achieved. The gate count of the PTMP is about 30K, and the die size is 7522mm*6107mm. The whole chip is designed and implemented with COMPASS 0.6mm HP CMOS cell library, and it is currently under fabrication through NSC/CIC MPC services.