標題: | 應用於三維電腦圖學中具有透視效果之紋理貼圖單元之設計 A Novel Processor Architecture for 3D Graphics Perspective Texture Mapping |
作者: | 許立群 Xu, Li-Qun 李鎮宜 Li, Zhen-Yi 電子研究所 |
關鍵字: | 紋理貼圖;描繪;消除鋸齒;透視;吞吐量;管線化;電子工程;Texture Mapping;Rasterization;Anti-aliasing;Perspective;Throughput;Pipeline;ELECTRONIC-ENGINEERING |
公開日期: | 1996 |
摘要: | 3D computer graphics has becoming more and more important in modern multimedia and virtual reality systems. In this area, texture mapping is one of the most successful techniques which can make images look more realistic and complex. In this thesis, a perspective texture mapping processor (PTMP) is designed and implemented to improve the texture mapping performance of computer graphics. The PTMP can give the proper effort of foreshortening on texture mapped polygon. The hardware of rasterization and anti-aliasing is incorporated into PTMP.The features of this design include modified four sided polygon scan-converter, logarithm space divider, and simplified algorithms for anti-aliasing. To enhance rendering speed and throughput, the fully pipelined architecture is designed. By analyzing data flows and operations, many resource sharing techniques can be utilized to reducehardware cost. The post layout simulation results show that the system can operate up to 71MHz. That is, the pixel rate is 17.85M pixels per second and 158.67K 10 * 10, Z buffered, polygon rate per second can be achieved. The gate count of the PTMP is about 30K, and the die size is 7522mm*6107mm. The whole chip is designed and implemented with COMPASS 0.6mm HP CMOS cell library, and it is currently under fabrication through NSC/CIC MPC services. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT854428001 http://hdl.handle.net/11536/62486 |
顯示於類別: | 畢業論文 |