應用階層式方塊比對演算法之動態影像預估處理器設計

Abstract

本論文提出一個應用階層式搜尋方塊比對演算法設計之動態影像預估處 理器，因架構設計上的考量，使得本處理器亦適用於全搜尋演算法，在應 用上更具彈性。為因應MPEG-2 MP@ML 即時編碼的要求，本架構採用了平 行化的設計，semi-systolic array 為主體的運算架構可使硬體使用率達 到 100%。整個架構設計可分為控制單元、記憶庫單元、二維處理陣列、 累加單元及比較單元等五個部份。與以往設計不同之處在於本架構將相鄰 搜尋區域重疊的資料再使用亦納入考量，只要增加少許硬體，便可避免相 同資料的重覆輸入，大幅降低輸入頻寬。此外，可調整的架構設計亦在考 量之內，藉由不同數目的晶片串接，可應用於大小不同的參考方塊之比對 與搜尋。與外界電路的傳輸介面也一併考慮於設計中。利用 0.6um Compass library 合成與佈局，並在 TSMC SPDM0.6um 製程技術下製作， 該晶片時脈速度經 IMS 測試可達 83.3 MHz，這個結果顯示此晶片可符合 MPEG-2 MP@ML 即時編碼的要求。 In this thesis, a VLSI architecture for motion estimation baed on a hierarchical-search block matching algorithm (HSBMA) is developed. The proposed architecture can deal with the full- search block matching algorithm(FSBMA) as well. To meet the real-time requirement of MPEG-2 MP@ML, parallelprocessing is in great demand. Adopting semi-systolic array (SSA) architecture, 100% hardware efficiency can be achieved within processingelement (PE) array. This proposed architecture mainly consists of fiveunits, namely control unit, memory bank unit, 2-D processing element array,summation unit and comparison unit. The key feature of this design is that the maximum possible reuse of overlapped search area pixels is considered,which can reduce the bandwidth of the frame memory interface. Also, scalabledesign is included. By cascading several chips, we can process the referenceblock with different sizes. Based on 0.6um Compass library and TSMC 0.6um SPDM process technology, clock up to 71.4 MHz can be achieved. The resultimplies that this chip can meet the real time requirement of MPEG-2 MP@MLencoding.