超薄介電層和粗糙複晶矽電極在記憶元件上之應用

Abstract

在此論文中,我們探討了如何提升動態隨機存取記憶體中電容器的電容 值.隨著記憶體密度的增加,單位記憶胞的面積必需隨之縮小,但為了免於 受到氦原子核的輻射而產生錯誤的資料,電容值不能隨之縮小,必需維持一 相對的數值.由平行板電容器的計算公式得知,有三種方法可以用來提生電 容器的電容值.在此論文中,我們僅就降低介電層的厚度和增加底電極板的 有效面積作一研究.首先是降低介電層的厚度.傳統應用於動態隨機存取記 憶體中電容器的介電層是[氧化矽/氮化矽/氧化矽],或[氧化矽/氮化矽]的 堆疊結構,它們是利用濕氧化氮化矽所得到的.對於薄的氮化矽,因為濕氧 的氧化能力太強,以致利用它氧化氮化矽所形成的堆疊介電層的厚度,已降 到它的極限值(等效氧化矽厚度約為55埃,它不適合用在16百萬位元的動態 隨機存取記憶體或更高的密度).因此我們提出了一種簡單且有效的方法, 更進一步地把傳統以氮化矽為主的堆疊介電層的等效氧化矽厚度降低,並 保有好的電性.此方法是將薄的氮化矽置入傳統的低壓高溫爐管中,在低壓 的氣氛中通入純的乾氧使之氧化.經由歐傑電子分析和蝕刻速率的分析可 以知道,利用此一方法可以得到極薄的[氧化矽/氮化矽/氧化矽]的堆疊結 構(等效氧化矽厚度可低到45埃以下).它和傳統在常壓下乾氧化薄的氮化 矽所得到的僅是[氮化矽/氧化矽]的堆疊結構非常地不同.因為低壓乾氧化 薄的氮化矽所得到的是[氧化矽/氮化矽/氧化矽]的堆疊結構,使得它比其 他介電層擁有高的可靠度和低的漏電流的特性.另外,本文也對乾氧化氮化 矽的壓力效應作一深入的探討,發現氧化壓力對介電層(原始氮化矽厚度 為60埃)厚度的關係有一轉折點的出現,並嘗試提出一個氧化機構加以解 釋.此外,我們也利用傅立葉轉換紅外線(FTIR)的光譜分析此一介電層,發 現它和濕氧化氮化矽具有相同的能譜位置,證實了它的上氧化層之組成與 傳統濕氧化氮化矽所得到的上氧化層相同.另一個提升電容器之電容值的 方法是增加底電極板的有效表面積,亦即在相同的光罩面積上,利用三維的 立體結構來增加電極板有效的表面積.因此,我們提出了一種製造粗糙複晶 矽電極板的技術.此方法是將複晶矽電極先經離子佈植及高溫活化後,再浸 入熱磷酸溶液中蝕刻.因為植入的磷離子經由高溫退火後會偏析至複晶矽 晶界以及在複晶矽晶界中有較多的晶體缺陷,造成在隨後的熱磷酸處理時, 在複晶矽晶界和晶粒有高的蝕刻速率比,以致在複晶矽表面形成很多的多 孔狀矽(porous-Si)及凹痕結構(engraved structures).我們利用掃瞄式 電子顯微鏡和穿透式電子顯微鏡分析蝕刻過的複晶矽表面及未蝕刻過的複 晶矽內部結構,證實了熱磷酸對晶界確實會作選擇性的蝕刻.此外,我們也 證明了雙層複晶矽結構在熱磷酸蝕刻中的重要性,因為它的晶界在兩層複 晶矽中不連續,以及存在於兩層複晶矽中的俱生氧化層(native oxide),都 可延長此雙層複晶矽被蝕斷的時間,並可提生表面積的增加倍率.這些具有 凹痕結構的複晶矽在經過標準的RCA清洗步驟處理後,會在表面形成微島狀 結構(micro-islands),亦即複晶矽上的凹痕被擴大了,這些微島狀結構更 有助於表面積的增加.經由實驗證明,過氧化氫,氨水,水的混合液(SC-1)是 造成複晶矽結構改變的主要溶液,這是因為它會蝕刻矽,因此把凹痕擴大 了.此外,我們也對磷酸的蝕刻溫度作一研究發現,當磷酸的蝕刻溫度愈高 時,電極板表面積的增加倍率反而變小.這是因為磷酸在愈高溫時,蝕刻速 率太快,造成複晶矽的晶界和晶粒的蝕刻速率比降低,並造成晶粒矮化,所 以有效表面積的增加倍率反而變小.另外,我們也發現雙層複晶矽結構中的 上層複晶矽愈厚時,有效表面積的增加倍率也愈大.最後我們結合快速熱氮 化步驟,低壓氧化氮化矽,及粗糙複晶矽,成功地製作一個具有高電容值,低 漏電流,高可靠度的電容器,可應用於未來高密度的隨機存取記憶體中. In this thesis, the applications of ultrathin dielectric and roughened poly-Si electrodes for the high-density dynamic random-access memory (DRAM) have been studied. With increasing the density of DRAM, the unit cell area must be reduced. However, the amount of charge stored on the capacitor must remain relatively constant from generation to generation to avoid the soft error causing by the alpha particles (He2+) radiation. From the calculating equation of the flat-type capacitor, there are three ways to enhance the capacitance. We only study the methods of reducing the thickness of dielectric films and enlarging the surface area of bottom electrodes. Firstly, to reduce the thickness of dielectric films is the most direct and efficient method to increase the capacitance. The conventional dielectric used for the DRAM's capacitors is the oxide/nitride/oxide (O/N/O) stacked structure which is formed by wet-oxidizing nitride films. The oxidation rate of wet oxidation to thin nitride films is very fast, resulting in that the thickness of stacked dielectric fabricated by wet-oxidizing thin nitride films have been lowered down close to the limit (the equivalent oxide thickness is about 55 A, which is not suitable for 16 Mb DRAM and beyond). Therefore, we propose an easy and efficient method to further reduce the equivalent oxide thickness of the nitride-based stacked dielectric. This dielectric is fabricated by oxidizing thin nitride at the low pressure ambient with dry O2 in a conventional low-pressure furnace. From the results of AES analysis and step-by-step diluted-HF etching profile, superthin O/N/O stacked dielectric can be achieved by low-pressure oxidizing thin nitride films (the equivalent oxide thickness can be lowered down below 45 A). This result exhibits big difference from that conventional oxidation of thin nitride films at atmospheric pressure, which only nitride/oxide (N/O) stacked dielectric formed. Owing to the O/N/O stacked structure, formed by low pressure oxidation of nitride films, it possesses high reliability and low leakage current as compared to other dielectric. Moreover, we have also studied the effects of oxidation pressure to the nitride films. It can be observed that there is a turn-around characteristics within the testing pressure and we propose a mechanism to explain this novel feature. In addition, the composition of the top oxide layer for the low pressure oxidation of nitride films has been confirmed by the FTIR specta and it exhibits the same composition of the top oxide for the wet oxidizing nitride films, which is resulting in the good electrical properties. Another method of enhancing the cell capacitance is to enlarge the surface area of bottom electrodes i.e. under the same masked area, 3-dimensional structure is utilized to enhance the surface area. We propose a method to roughen the poly-Si, in which poly- Si is firstly phosphorus-implanted, activated, and then immersed into hot phosphoric acid (H3PO4). There are porous-Si and engraved structure on the grain surface and grain boundaries, respectively, for the doped poly-Si etched by H3PO4 solution. The segregation of the phosphorus atom and crystal defects at the grain boundaries are surmised as the main cause, resulting in the high selective etching ratio of grain boundaries to grain for the H3PO4 solution. These results have been confirmed by the top-view SEM photograph of H3PO4-etched poly-Si and plan-view TEM photograph of unetched poly-Si. Moreover, the double-layered poly-Si structures are demonstrated to be required for the increment of cell capacitance. The bottom electrodes with double-layered poly-Si exhibit slow increment of sheet resistance, because of the native oxide between the two poly-Si layers and the unsuccessive grain boundaries of the two poly-Si, which can lengthen the broken time. After standard RCA cleanup procedures, the poly-Si with porous-Si and engraved structure will be transferred into micro-islands structures, which can further enhance the surface area of storage-nodes. It has been proved that the mixed NH4OH-H2O2-H2O (SC-1) solutions is the dominate one to change the poly-Si structure because the SC-1 solutions can etch Si and then enlarge the width of the engraved structures. In addition, there are large grains and deep cavities on the surface of storage-nodes, etched by H3PO4 solution at lower temperature, which can achieve higher increment factor of the cell capacitance. In contast, only small and short grains appear on the poly-Si, etched at higher temperature, resulting in the reduction of the increment factor. At higher etching temperature, the etching rate is too fast, resulting in the reduction of the etching selectivity for the grain boundaries to grains. Moreover, the thicker top poly-Si of the double-layered structure is, the more increment factor of the cell capacitance does the capacitor exhibit. Finally, with combinations of the rapid thermal nitridation (RTN), low pressure oxidation of thin nitride films, and roughened poly-Si electrodes, we have successfully fabricated a capacitor with high capacitance, low leakage current, and high reliability, which satisfies the requirements of future high-density DRAM's applications.