離散餘弦轉換之低成本處理器設計

Abstract

在許多的訊號處理的應用上,離散餘弦轉換(DCT)扮演一個很重要的沔色 而即時一些應用, 如MPEG-2解壓縮器, 帶動了高速與高價格設計之發展。 然而, 就最近很熱門的數位相機(DSC)而言, 他並不需要高速的離散餘弦 轉換器,但是一般設計然常是用昂貴的DSP 處理器或高速的硬體來達成, 以致於成本居高不下。本論文提出一個適合於低速應用之低價格處理器設 計。 本設計中主要基於"以加法器為主的分散式算術(Adder-based DA)" 架構, 他只需要加法器、移位器(shifter)與繞線就可以完成。我們使用 加法器與移位器,設計了一個特別適合於轉換運算之低價格資料處理單元 。配合一個透過最佳化設計的控制器來控至整個離散餘弦轉換的運算, 並 追求高硬體使用度與提高效能。並且透過運用原來存在於系統中的資源, 整個設計更加的便宜。 設計的結果與分析, 本設計的成本低於一個 16*16 的乘法器, 而效能相當於一個相對上非常昂貴之 DSP 處理器的一 半,且能符合數位相機對於離餘弦轉換運算的要求。 DCT/IDCT are useful in a number of signal processing applications, includingdata compression of image, video and audio signals. The real-time applications,such as MPEG-2 decoder, motivate the dedicated hardware design for DCT/IDCT with high speed performance, but high cost. However, the digital-still-camera(DSC) is a very hot topic in commercial products in recent year. The DCT operation is not required to have high speed response in the DSC application, but it is always implemented by the DSP processor or the dedicated hardware, that result high cost. To have a low cost design for DCT that will fit to the system of the low speed application. A novel design of low cost processor core for DCT is proposed in this thesis. The design is based on the 本設計的成本低於一hm which needs just adder, shifter and routing. A datapath with simple hardware is designed for the operation of transforms. And a controller, which is optimized by signed-digit and subexpression sharing to reduce the cycles of computation, generates the control signals to the datapath for performing the function. The hardware design to process DCT always exists in the system with RAM or processor. The resources of RAM in a system could be shared by this design for DCT, that reduces much cost. The cost of the proposed design is less than a 16x16 multiplier, and the performance is about a half of the DSPprocessor TI TMS320C3X and fits to the requirement of DCT operation in DSC application.