使用質數分解理論之 餘旋轉換/逆餘旋轉換 處理器設計

Abstract

離散餘弦轉換，已經被廣泛的運用在各種訊號處理上，像是影像壓縮、語音壓縮等，為了達到即時的目的，有許多快速的理論與研究被提出，但是這些研究大部分都只侷限在一維或是二維的領域上，且可處理的點數都是固定的，這對使用者來說，容易造成彈性不足的問題。 針對這個問題，本論文提出一個可擴充，且參數化的餘弦 / 逆餘弦轉換處理器架構，利用質數分解的理論將一維的餘弦轉換分解成二維，則這個架構就可以同時處理一維、二維的餘弦 / 逆餘弦轉換，而且具有可擴充、運算單元規則的特性。同時，我們也會將這個架構實現成晶片。 我們以TSMC 0.35um 的製程製造這顆晶片，其操作頻率為45.5M Hz，使用CIC的標準封裝，100 LD CQFP， 晶片的面積為3.15 3.15 。

DCT ( Discrete Cosine Transform ) has been widely used in digital signal processing , especially in image and audio processing. Although a large number of papers have been proposed to meet the real-time requirements, most of them can only deal with either 1-D or 2-D DCT/IDCT and the fixed-length DCT/IDCT. In order to increase the flexibility, this thesis proposes a scalable, parameterized DCT/IDCT processor using Prime-Factor Algorithm (PFA). The proposed architecture can perform both 1-D and 2-D variable length DCT/IDCT and features high degree of regularity and modularity. Finally, a prototype chip has been built using TSMC 0.35mm CMOS technology. The chip is packaged by 100 LD CQFP and can be operated at 45.5 MHz.