應用於即時數位視訊編解碼系統之高效能正反離散餘弦轉換架構與設計方法及相關計算機輔助軟體設計

Abstract

離散餘弦轉換(DCT)及其反轉換已經廣泛的運用在許多低位元率的視訊壓 縮孤統而且已成為許多國際標準的核心部份。在高畫質數位電視及更高取 樣速率的應用中，高效能的離散餘弦轉換處理器對高品質的多媒體通訊是 十分重要的。在本論文中，我們先提出一個新的使用精確邊緣匹配向量量 化預測器的頻域分類向量量化演算法來說明離散餘弦轉換在影像處理運用 上的有效性，這個演算法在主觀和客觀上皆優於現存的演算法。之後，基 於一個新的系統化設計方法及內嵌式離散餘弦轉換模組的系統要求，我們 提出了一個應用於數位及時編解碼視訊系統的高效能二維正反離散餘弦轉 換架構。這個架構主要包含了七個低硬體成本的常數乘法器及分時多工乘 法累加器，而且具有無轉置動作，低通訊複雜度，低輸出入頻寬，低面積 時間複雜度(area-time complexity)和適合用於超大型積體電路的製作等 等迷人的特性。和傳統的架構比較，所提出的架構不僅能減少系統整合的 硬體成本而且能更容易的達成即時編碼的要求。此外，我們更提出了一個 新的多路徑搜尋的遞迴多常數乘法(MCM)的演算法來最佳化離散餘弦轉換 架構中的常數乘法器。就我們所知，這個演算法優於現存於文獻中的任何 演算法。在TSMC SPDM 0.6mm製程技術之下，我們利用COMPASSTM 0.6mm高 性能的標準元件 (Standard Cells) 製作此架構，此架構使用了100K電晶 體，晶片核心(core)大小為3.9mm x 4.8mm，即18.71 mm2。而模擬結果顯 示本架構之晶片時脈速度可以達到100MHz，這意味了本架構不但可以應用 於許多數位編解碼視訊系統，而且也可以達成即時(real-time)編解碼的 要求。 Discrete cosine transform (DCT) has been widely used in the implementation of low bit rate codecs for video compression and become an integral part of several international standards. With the imminent arrival of HDTV and the considerably higher sample rates applications, high throughput processors dedicated to DCT are of great importance to achieve the high-quality multimedia communication. In this thesis, first, we present a new DCT domain classified vector quantization (CVQ) algorithm with accurate side match VQ predictor to demonstrate the effectiveness of DCT in many image processing applications. This algorithm outperforms the previously proposed algorithms subjectively and objectively. Then, based on a new systematic design methodology and the system requirements of an embedded DCT module, a high throughput 2D-DCT/IDCT VLSI architecture is proposed for the applications of a real-time digital video codec system. The proposed architecture mainly consists of seven cost coefficient constant multipliers and time-multiplexed multiplieraccumulators. It also possesses the appealing properties such as no transpose operation, low communication complexity, low I/O bandwidth, low area-time complexity and very suitable for VLSI implementation. As compared with conventional architectures, this architecture not only reduces the system integration hardware cost but also achieves the real-time encoding requirement more easily. Moreover, a new multiple constant multiplication (MCM) recursive algorithm with multi- path search strategy is proposed to optimize the constant multipliers used in the proposed DCT/IDCT architecture. To our knowledge, this algorithm outperforms any existing algorithms in literature. Based on TSMC SPDM 0.6mm process technology, we use COMPASSTM 0.6mm high performance cell library to implement the proposed architecture. It integrates about 100k transistors in a 3.9mm x 4.8mm, i.e. 18.71mm2, silicon area. Simulation results show that clock rate up to 100Mhz can be achieved, implying that the proposed architecture can meet the real-time requirement of many digital video codec systems.