十六位元數位類比轉換器的設計

Abstract

這篇論文描述一個可用在音響應用的十六位元數位至類比轉換器的設計. 為了達成音響應用所要求的高解析度, 除了超取樣的技巧外,和差調變的 技巧也被運用於此設計中, 這個十六位元的數位至類比轉換器是由一個串 聯輸入並聯輸出器,一個線性內插器,一個二階一位元的和差調變器和一個 電流模式的半數位重建濾波器所組成.串聯輸入並聯輸出器收集序列輸入 的十六位元數位資料,然後以44.1kHz的速率輸出這些十六元的數位資料至 下一級的線性內插器. 線性內插器利用線性內插的方式達到超取樣的功 能. 超取樣比為256. 超取樣後的十六位元數位資料經由二階和差調變器 的調變產生一串的一位元資料流. 最後,利用半數位重建濾波器當做數位 至類比的界面和低通濾波器來得到想要的類比輸出. 這個十六位元的數位 至類比轉換器的數位部分,也就是串聯輸入並聯輸出器,線性內插器,二階 的和差調變器已經藉由現場可規劃閘陣列(FPGA)的方式被實現,而半數位 重建濾波器則是已經被製造,利用0.6微米的互補式金氧半導體單層多晶矽 雙層金屬的製程. 它的晶片面積為2700x 2000 m^2 包括 pad.這個晶片使 用一個5伏特的電源,消耗的功率為12毫瓦. This thesis describes the design of a 16-bit Digital-to-Analog converter(DAC) for the audio application. The technique of noise shaping with sigma-delta modulation in addition to oversampling is used to achieve high resolution conversion of relatively low bandwidth audio signal. The 16-bit DAC consists of a serial-in-parallel-out(SIPO), a linear interpolator, an one-bit 2nd-order sigma-delta modulator, and a current-mode semi-digital reconstruction filter.The SIPO collects the serial 16-bit digital inputs and transmits them at44.1kHz to the linear interpolator. The interpolator performs the function of oversampling by the means of linear interpolation. The oversampling ratio(OSR) is 256. The oversampled 16-bit digital inputs are then modulated by the 2nd-order sigma-delta modulator to be a series of one-bit bit stream. Lastly, the semi-digital reconstruction filter is employed to be a digital-to-analog interface and a low-pass filter to get the desired analog output.The digital part of this 16-bit DAC, i.e. the SIPO, linear interpolator, 2nd-order sigma-delta modulator, has been implemented in a FPGA(Field Programmable Gate Array). The current-mode semi-digital reconstruction filter has been implemented by the 0.6 um SPDM CMOS technology. Its chip size including pads is 2700 x 2000 um^2. The chip uses a single 5V power supply and dissipates power 12mW.