P通道金屬半快閃式記憶體中不同程式化的可靠性評估

Abstract

熱載子效應及其衍生的元件可靠性問題已成為目前快閃式記憶體元件設 計的主要考量。目前大部分有關於快閃式記憶體的研究大多偏重於n通道 結構,較少研究p通道的結構。在本論文中﹐我們將針對p型通道快閃式元 件可程式化的特性做一比較性的研究﹐其中可程式化的方法可分為通道熱 電子的注入(Channel Hot Electron Injection)以及能帶至能帶間(Band- to-Band)所產生的熱電子注入兩種。其次﹐我們將研究在程式化操作中熱 電子所引起的可靠性問題﹐而這些問題都歸因於界面狀態的產生(Nit)及 氧化層傷害(Qox) 。因此﹐在研究快閃式記憶體元件的可靠性問題時﹐如 何決定此二物理量的空間分佈便成為首要工作。首先﹐我們使用一種簡單 及精確的profiling技術來決定在程式化偏壓操作條件下所引起的界面狀 態及氧化層傷害的空間分佈﹐根據此空間分佈﹐我們可以進一步深入研究 元件的退化機制。在程式化操作之下﹐我們發現氧化層傷害將造成嚴重程 式化特性的退化﹐同時﹐我們發現界面狀態(Interface State)的產生是 造成程式化速度延遲的主要機制。此外﹐我們針對最佳能帶至能帶間可程 式化的方法進行深入研究並發現降低汲極電壓可有效改善元件的可靠性。 最後﹐我們針對p 型通道快閃式元件在兩種不同程式化所引起的可靠性問 題作一個比較﹐以了解各種方法的優缺點。 Hot-carrier injection induced device reliability has been a major concernin modern flash memory device design. Most of the reliability studies on flash memory have been paid on n-channel cell structure, quite few deal withthe reliability of a p- channel cell. In this thesis, we have made a comparative study of the p-channel flash cell reliability by studying its programming characteristics with different schemes which include channel hotelectron injection (CHEI) and band-to-band (BTB) induced hot electron injection operating schemes. Next, we studied the hot-electron stress inducedreliability problem during program operation. These reliability problems aredue to the generation of interface state and oxide trap charge. The profilingof these two oxide damages has played a major part for the study of flash memory reliability issues. In this work, first we use a simple and accurateprofiling technique to determine the lateral distribution of stress induced interface state and oxide charge in two programming bias conditions. Based onthe extracted profiles of interface state and oxide trap charge, the degradation mechanisms of flash memories can be understood more clearly.Afterthe stress of flash memories at the programming bias, we observed that the oxide damages will retard the programming characteristics seriously and alsofound that interface state generation is the dominant mechanism for the delayof programming speed. Besides, the scheme of optimum BTB program bias voltagefor achieving better reliability has been studied. We found that the lower the drain voltage for BTB programming, the better the device performance. Finally, the reliability of p-channel flash memories during programming operation has also been discussed.