矽化鈦閘極結構對薄閘極氧化層的影響

Abstract

在本論文中,我們提出展新的閘極結構應用於自準矽化鈦過程。首先,我們 探討在傳統急速加溫退火自準矽化鈦製程中,溫度對複晶上片電阻及電特 性的影響。在複晶上片電阻和閘極電特性的折衷下可以找出適當的製程溫 度。基於實驗結果,在傳統自準矽化鈦中,第一步最適當的溫度是650oC 而 第二步最適當的溫度是850oC。 更進一步,我們提出不同的閘極結構來減 少傳統自準矽化鈦製程所帶來的退化,比如極大的漏電流(20-30 pA),及低 氧化層崩潰。同時,我們又提出離子活化和自準矽化鈦一起完成製程的技 術。從實驗結果中,我們很清楚的知道在疊形結構配合新的製程能顯現出 比傳統製程更低的漏電流(7-10 pA)及在氧化層有較好的可靠度。 In this thesis, a novel gate structure using self-aligned TiSi2 (Ti-salicide)process has been proposed. First, we investigated the effect of temperature on the sheet resistance and the electrical characteristics of Poly-Si gate for the conventional Ti-salicide process using rapid thermal annealing (RTA). The optimized temperature for the tradeoff between the sheet resistance and electrical characteristics on Poly-Si gate were observed. Based on the results, the optimized temperature in the first step is 650°C and the second step is 850°C. Furthermore, we proposed a new gate structure to reduce the degradation due to the conventional Ti-salicide process, such as high leakage current (20-30 pA ) and low oxide breakdown. At the same time, a novel fabrication process, which combines dopant activation with Ti-salicide process, was also proposed. From experimental results, the stacked structure together with the novel process showed the lower leakage current (7-10 pA) and better oxide reliability than that of conventional gate.