高密度動態隨機存取記憶體用之金氧半電容器之研究

Abstract

隨著記憶體密度的增加，單位記憶胞的電容值會隨之而減低，此問題對未 來動態隨機存取記憶體是一項很嚴重的限制。但為了免於受到氦原子核的 輻射而產生錯誤的資料，電容值必須維持一相當的數值。由平行板電容器 的計算公式得知，有三種方法可以用來提升電容器的電容值。在此論文中 ，我們僅就增加底電極板的有效表面積與使用高介電常數之材料當絕緣層 這兩方面作一研究。一個提升電容器之電容值的方法是增加底電極板的有 效表面積，亦即在相同的光罩面積上，利用三維的立體結構來增加電極板 有效的表面積。因此，我們提出了一種製造複晶矽電極板的技術。此方法 是將複晶矽電極板先經過磷離子佈植及高溫活化後，再浸入熱磷酸溶液中 蝕刻。因為植入的磷離子經由高溫退火後會偏析至複晶矽晶界及在複晶矽 晶界中有較多的晶體缺陷，造成在隨後的熱磷酸處理時，在複晶矽晶界和 晶粒有很高的蝕刻速率比，以致在複晶矽表面形成很多的多孔狀矽。此外 ，我們也證明了多層複晶矽結構可用來提升記憶胞電容器的電容值。多層 複晶矽結構顯示了片電阻的增量減緩，因為存在於兩層複晶矽中的俱生氧 化層，以及它的晶界在兩層複晶矽中不連續，都可延長此雙層複晶矽被蝕 斷的時間。這些具有凹痕結構的複晶矽在經過標準的RCA清洗步驟處理後 ，會在表面形成微島狀結構，這些微島狀結構更有助於表面積的增加。在 熱磷酸蝕刻之前，我們使用快速退火與爐管退火的方式作活化處理，藉由 此種方式可以得到更小的晶粒尺寸。這種合併快速退火與爐管退火的方式 ，可以使用在未來更小記憶胞尺寸的動態隨機存取記憶體中。另一種增加 電容值的方式是使用高介電常數的材料做絕緣層。這些材料的特性可具有 更簡單的製程方式及更低的製造成本。我們使用一種新的沉積方式，液態 源霧化化學沉積(LSMCD)，來沉積一些高介電常數材料，如鈦酸鋇及鈦酸 鍶鋇。這種沉積方法比自旋沉積具有較佳的平整度，適於更高的整合度， 由於是採用單一液態源，液態源霧化化學沉積有較佳的化學計量比。在本 論文中，我們採用這種沉積方式製作出的堆疊式電容器，具有良好的電性 與結晶特性，並簡化了製程的複雜性。 經由液態源霧化化學沉積程序所 製作出的堆疊式電容器在將來將有極佳的發展潛力。 Reduction of cell capacitance, resulting from the memory cell miniaturization, is one of the most serious problems that limit further dynamic random access memory (DRAM) integration. However, the amount of charge stored on the capacitor has to be maintained constant from generation to generation to prevent the soft error from alpha particles (He2+) radiation. By the equation of the flat-type capacitor, there are three ways to enhance the capacitance. In this thesis, enlarging the surface area of the storage-nodes and utilizing high dielectric constant materials are investigated for high density DRAMs.A method of enhancing the cell capacitance is to enlarge the surface area of bottom electrodes, i.e. under the same masked area, three- dimensional structure is utilized to enhance the surface area. A novel technique of roughened poly-Si electrode is issued. Poly-Si is firstly phosphorus-implanted, activated, and then immersed into hoto hot phosphoric acid (H3PO4). There are porous-Si and engraved structure on the grain surface and grain boundaries, respectively, after H3PO4 treatment. The segregation of the phosphorus atoms and crystal defects at the grain boundaries result in the high selective etching ratio of grain boundaries to grain for the H3PO4 treatment. Moreover, the multi-layered poly-Si structure is demonstrated to be required for the increment of cell capacitance. The multi- layered poly-Si as the bottom electrode shows slow increment of the sheet resistance, because of the native oxide between the two poly-Si layers and the noncontinuous grain boundaries of the two poly-Si layers, which can also lengthen the broken time. After standard RCA cleanup procedures, the poly-Si is transferred into micro islands structures, which can further enhance the surface area of storage-nodes. The rapid thermal annealing (RTA) and furnace annealing (FA) are proposed before H3PO4 treatment, by which smaller grain size can be obtained. This RTA+FA process can be accommo smaller cell size of DRAMs. Another way to increase the capacitance is using high dielectric constant material. The characteristics of much higher dielectric constants compared with conventional constants is expected to five fully planarized storage capacitors, leading to a simple process with lower fabrication costs. A novel technique for the deposition of high dielectric materials such as BaTiO3 (BTO) and Ba,SrTiO3 (BST) is called the liquid source misted chemical deposition (LSMCD) method. LSMCD has better step coverage than the spin-on method, which his essential for higher integration. LSMCD also allows the controllability of stoichiometry because of the single liquid sourece. In this chapter, the fabrication and electrical properties of the high dielectric constant stacked capacitor (BTO and BST) are demonstrated by the LSMCD technique. The fabricated capacitors display excellent electrical properties. The development of this process offers significant simplification for the fabrication of high dielectric constant materials. These materials deposited by the proposed deposition technique are very promising for integrating BST or BTO in gigabit-scale DRAMs.