新型互補式金氧半射頻接收器前置電路設計與分析

Abstract

本篇論文的主旨在於闡述射頻接收器前置電路的設計方法及製作技 術。論文中包含下列四個主要部分﹕（1）在矽基座上應用於射頻電路的 方形迴旋電感器的模型、設計、及分析﹔（2）3V 900MHz 的金氧半互補 式帶通放大器的設計與分析﹔（3）新型互補式金氧半四象限類比乘法器 的設計與實現及其在 2GHz 射頻下轉換混波器的應用﹔（4）應用於行動 通訊系統的 900MHz 互補式金氧半射頻接收器前置電路設計。 首先， 本論文中針對矽基座上的平面迴旋電感器提出一個多節式的等效電路模型 。在此模型中，迴旋電感器的特性是針對每一個不同的線圈來模擬的，如 此可顧及電感器中的分散式效應，而模型的準確度也可以增加。除此之外 ，在先前的文獻中沒有建立適當模型的電感器基座側向電阻在本論文中也 得以建立公式化的模型。許多不同外型參數的電感器也以零點八微米的互 補式金氧半製程來製作以驗證此模型的準確度。其量測結果顯示此模型 在6GHz的範圍內皆可達到相當良好的準確度。另外，根據此模型，本論文 中也提出了一個針對特定電感器特性來設計電感器外型參數的方法。此種 方法可以不需重複的試驗而得到一個最佳特性的電感器。 其次，本論 文中提出了一個結合低雜訊放大器和帶通濾波器功能的帶通放大器。此帶 通放大器是根據900MHz無線通訊系統的規格而設計的。此放大器中使用正 迴授品質因數增強技術來改良調諧放大器的低品質因數的缺點。另外也使 用了密勒電容式微調方法來來補償製造時的中心頻率誤差。使用這個高品 質因數的帶通放大器將可以省略接收器電路中的外接帶通濾波器。此帶通 放大器以零點八微米的互補式金氧半製程來製作。量測結果顯示，在3V的 電壓之下，此放大器的品質因數可在2.2及44之間做調整。在品質因數等 於30時，此放大器的中心頻率可在869-893MHz之間做調整，而功率增益 為17分貝，雜訊指數為6分貝，輸出一分貝截止點為-30dBm，輸入端三諧 交越點為-14dBm，功率消耗為78mW。 接下來，本論文中提出了一個新 型的四象限類比乘法器。本乘法器中使用差動輸入訊號到一組混合器中， 藉此得到乘法器的功能。運用此種架構所得到的乘法器有良好的性能，也 以零點八微米的互補式金氧半製程來製作。實驗結果顯示，此乘法器 在1.2伏特的電壓下的最大輸入電壓為500mV，此時的線性度誤差為0.89% ，總諧波失真為1.1%，頻寬為2.2MHz，而電流消耗為2.3mA。另外，根據 此乘法器的架構，本論文中也設計了一個射頻的下轉換混波器，並且 以0.5微米的互補式金氧半製程來製造。實驗結果顯示，此混波器在3伏特 的工作電壓及2dBm的本地震盪下，其轉換增益為-1分貝，輸入頻寬為2.2 GHz，輸出頻寬為180MHz，雜訊指數為22分貝，輸出一分貝截止點為-9dBm ，輸入端三諧交越點為+7.5dBm，電流消耗為21mA。 最後，根據前述 的帶通放大器和混波器架構，本論文中設計了一個900MHz高整合度的影像 拒斥型接收器前置電路。此接收器以0.5微米的互補式金氧半參數來模擬 驗證。模擬結果顯示，此接收器在3伏特的工作電壓，850MHz、0dBm的射 頻本地震盪，及100MHz、0dBm的中頻本地震盪之下，其功率增益為36分貝 ，雜訊指數為5.7分貝，輸入端三諧交越點為-12dBm，輸出一分貝截止點 為-33dBm，輸入端阻抗匹配為-10分貝，而功率消耗為390mW。 經過模 擬和實驗證實，本論文中所發展的電路將可應用於一個高整合度、全互補 式金氧半電晶體的無線通訊統之中。如此將可以實現一個低價格、小體積 的行動通訊裝備。在未來將針對其他的射頻元件做整合而成為一個完整的 收發器。 In this thesis, the design methodology and implementation techniques of CMOS RF receiver front-end circuits are presented. There are four parts in this research, including (1) the modeling, design, and analysis of square spiralinductors on silicon substrate for radio frequency applications; (2) the designand analysis of a 3-V 900-MHz CMOS bandpass amplifier for wireless applications;(3) the design and implementation of a new CMOS four-quadrant analog multiplierand its application to 2 GHz RF downconversion mixer; (4) the design of a 900-MHz CMOS RF receiver front-end circuits for the mobile communicationapplications. At first, a multi-section equivalent circuit model for the planar squarespiral inductors on silicon substrate is proposed. In the proposed new model,the spiral inductors are characterized turn-by-turn to consider the distributioneffect and increase the model accuracy. Moreover, the lateral substrateresistances of the inductors, which are not well formularized previously, are alsomodeled and formularized. The resultant model is totally formularized withoutfitting parameter. Several inductors have been designed and fabricated by 0.8umdouble-metal CMOS technology. It has been shown that the model calculation resultsare consistent with the measured results with a good accuracy up to 6 GHz. Thusthe proposed new model can be used to characterize the integrated square spiralinductors for RF applications. Based upon the proposed model, a design methodologyis proposed to design an inductor with the specified characteristics. Thismethodology can be used to efficiently design an optimal inductor without longiterative tuning of inductor parameters. Secondly, a new bandpass amplifier which performs both functions of low-noise amplifier (LNA) and bandpass filter (BPF), is proposed for the applicationof 900 MHz RF front-end in wireless receivers. In the proposed amplifier, thepositive-feedback Q-enhancement technique is used to overcome the low-gain low-Qcharacteristics of the CMOS tuned amplifier. The Miller-capacitance tuningscheme is used to compensate for the process variations of center frequency.Using the high-Q bandpass amplifier in the receivers, the conventional bulky off-chip filter is not required. An experimental chip fabricated by 0.8um N-welldouble-poly-double- metal CMOS technology, occupies 2.6□2.0 mm2 chip area. Undera 3 V supply voltage, the measured quality factor is tunable between 2.2 and 44.When the quality factor is tuned at Q = 30, the measured center frequency of theamplifier is tunable between 869 MHz and 893 MHz with power gain 17 dB, noisefigure 6.0 dB, output 1dB compression point at -30 dBm, third-order inputintercept point at -14 dBm, and power dissipation 78 mW. Thirdly, a new structure for CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set ofcombiners, the multiplication function can be implemented. Based on the proposedstructure, a low- voltage high-performance CMOS four-quadrant analog multiplieris designed and fabricated by 0.8 □m N-well double-poly-double- metal CMOStechnology. Experimental results have shown that, under a single 1.2 V supplyvoltage, the circuit has 0.89% linearity error and 1.1% total harmonicdistortion under the maximum-scale input 500 mVP-P at both multiplier inputs.The -3 dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using theproposed multiplier as a mixer-core and connecting a newly designed outputbuffer, a CMOS RF downconversion mixer is designed and implemented by 0.5umsingle-poly-double-metal N-well CMOS technology. The experimental results haveshown that, under 3 V supply voltage and 2dBm LO power, the mixer has -1 dBconversion gain, 2.2 GHz input bandwidth, 180MHz output bandwidth, and 22 dBnoise figure. Under the LO frequency 1.9 GHz and The total dc current 21 mA,the third-order input intercept point is +7.5 dBm and the input 1 dB compressionpoint is -9 dBm. Finally, based on the proposed new RF bandpass amplifier and mixer structure, a 900MHz CMOS image rejection receiver front- end circuits isdesigned. The receiver circuit is designed and simulated by using 0.5um N-welldouble-poly-double-metal CMOS technology. The overall chip area is 2.54mm x2.54 mm. The HSPICE simulation results have shown that, with 850 MHz 0 dBm RFLO and 100MHz 0 dBm IF LO inputs under 3V supply voltage, the CMOS RF receiverfront-end circuit has the gain of 36 dB, the noise figure of 5.7 dB, the thirdorder input intercept point of -14 dBm, the input 1 dB compression point of -33dBm, the input S11 of -10dB, and the power dissipation of 390 mW. It is believed that the proposed high performance RF receiver front- end circuits can be applied to an all-CMOS wireless communication system. Thus alow-cost small-size mobile equipment can be implemented. Further research onthe integration of other transceiver components will be conducted in the future.