完整後設資料紀錄
DC 欄位語言
dc.contributor.authorSu, N. C.en_US
dc.contributor.authorWang, S. J.en_US
dc.contributor.authorChin, Alberten_US
dc.date.accessioned2014-12-08T15:07:53Z-
dc.date.available2014-12-08T15:07:53Z-
dc.date.issued2010en_US
dc.identifier.issn1099-0062en_US
dc.identifier.urihttp://hdl.handle.net/11536/6216-
dc.identifier.urihttp://dx.doi.org/10.1149/1.3257607en_US
dc.description.abstractThis study demonstrates the feasibility of producing a ZnO thin film transistor (TFT) using hafnium-lanthanum-oxide (HfLaO) as the gate dielectric. By integrating high-kappa HfLaO with an amorphous ZnO channel, the resulting HfLaO/ZnO TFTs display a low threshold voltage (V(T)) of 0.28 V, a small subthreshold swing (SS) of 0.26 V/dec, an acceptable mobility (mu(sat)) of 3.5 cm(2)/V s, and a good I(on)/I(off) ratio of 1 X 10(6). The SS heavily depends on the HfLaO/ZnO interface charges, a property which is related to the degree of crystallization of ZnO. The low VT and the small SS allow device voltage operation below 2 V for low power application. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3257607] All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleA Low Operating Voltage ZnO Thin Film Transistor Using a High-kappa HfLaO Gate Dielectricen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/1.3257607en_US
dc.identifier.journalELECTROCHEMICAL AND SOLID STATE LETTERSen_US
dc.citation.volume13en_US
dc.citation.issue1en_US
dc.citation.spageII8en_US
dc.citation.epageII11en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000271668500013-
dc.citation.woscount10-
顯示於類別:期刊論文


文件中的檔案:

  1. 000271668500013.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。