利用實驗設計改善積體電路閘極缺陷

Abstract

台灣半導體產業目前正面臨大陸晶圓廠的競爭,因此為了保持自身的競爭優勢, 台灣各家半導體廠,尤其是生產Dram 的製造商,無不致力於提昇晶圓良率,以期能在最短的時間內快速提昇產品良率。有鑒於目前業界在晶圓缺陷分析上仍使用傳統的實驗方法,即採取一次調動一個因子的設計法來進行實驗,此種實驗結 果並不能保證可以找到最佳解且實驗時間相當冗長;因此本研究主要目的是利用三因子兩水準之隨機集區法( randomized complete block design ; RCBD )來進行積體電路閘極缺陷( defect )的改善,此閘極缺陷問題發生的原因是在矽化鎢( Wsix )沉積後之表面形成小凸起的現象,導致閘極線路製作完成後發生嚴重的線路橋接(Bridge)現象,以至讓晶圓良率降低,最嚴重時將會降至3 %左右。由於目前許多中外文獻中並未見到探討本論文所提出的缺陷問題,故本研究在無太多參考資訊的情況下,運用穿透式電子顯微鏡( transmission electron microscopy,TEM )的分析儀器,發現閘極缺陷是發生在多晶矽與Wsix製程之間,因此從切片資料找出鹽酸/雙氧水/水 (Hydrochloric Peroxide Mixture, HPM)混酸、氧化層蝕刻以及多晶矽沉積等三個影響良率之實驗實驗因子,並將HPM 混酸之製程參數設定為”使用HPM”、”不使用HPM”兩個水準,氧化層蝕刻之製程參數設定為”HF vapor (100% HF)”、”Dilute HF(H2O2: HF = 200:1)“兩個水準及多晶矽沉積之製程溫度設定在” 高溫1050°C (high temp.)” 、” 低溫575°C (low temp.)”兩個水準,而集區變數為廠區,亦設定兩個水準,來進行整個實驗規劃且每組實驗條件進行8次,並利用Mintab統計軟體進行分析,順利找出解決閘極缺陷之最佳配方是”使用HF vapor(100% HF)進行氧化層蝕刻”。根據上述最佳配方運用於量產產品上,最後使得產品之良率穩定在82~84%高良率水準上,使公司產品更具市場競爭力。

Semiconductor industry in Taiwan currently has faced strong competition from the wafer foundry companies in Mainland China, therefore, to retain its own competitiveness in the market, all the wafer foundry companies in Taiwan are dedicating their great efforts on the improvement of semiconductor manufacturing yield rate, it is hoped that the product yield rate can be enhanced in short term, this is especially true for manufacturers of DRAM. Currently, traditional experimental method is used in the industry to perform wafer defect analysis, that is , one factor is adjusted each time to conduct the experiment , this method does not guarantee that it can find the optimum solution, besides, it is a very tedious process; therefore, this study aims at using Randomized Complete Block Design (RCBD) method with three factors and two levels for each factor to improve the gate electrode defect of integrated circuits. The gate electrode defect forms as small bumps on the surface after WSix is deposited, it leads to serious circuit bridge after gate electrode circuit is completely manufactured. The wafer yield rate thus could drop by 3% at the worst case . Since the defect problems mentioned in this study are not yet investigated by literature over the world, therefore, there are very few information we can refer to. Transmission electron microscopy (TEM) was used and the gate electrode defect appears between the processes of polycrystalline silicon and WSix. Therefore, Three experimental factors affecting yield rate from the sectioning sample are : HCL/H2O2/ H2O (Hydrochloric Peroxide Mixture, HPM)mixed acid , oxide etch and polycrystalline silicon deposition. Experimental planning by setting the process parameters of HPM mixed acid as two levels of ”Using HPM” and ”Not using HPM”; setting the process parameters of oxide etch as two levels of ”HF vapor (100% HF)” and ”Dilute HF(H2O2: HF = 200:1)“ ; and setting the process temperatures of the polycrystalline silicon deposition as two levels of ”1050°C (high temp.)” and ”575°C (low temp.)” .The block variable is the plant area , it has two levels for the whole experimental planning, each experimental condition is performed 8 times. In the mean time, the Mintab statistical software is used for analysis, we eventually find an optimum recipe for solving the gate electrode defects, that is , ”use HF vapor (100% HF)for the oxide layer etching ”.By using the above optimum recipe in the mass production, we are able to obtain a stable yield tare of 82%~84%,it also help to make the company product more competitive.