在動態指令再利用中改良指令之分派

Abstract

There are many instructions that would be executed repeatedly, and the concept of dynamic instruction reuse is to buffer the result, which executed previously and reuse the result if it can be reuse, and thus reduce the total number of instruction executed. The purpose of this research is to apply this concept to the superscalar architecture and we assumed that the dynamic instruction reuse to be incorporated into the general and simplified superscalar architecture. Under this basic assumption we found that there are problems incorporating dynamic instruction reuse into superscalar architecture. The first problem is the instruction dispatch problem.We know that superscalar architecture decodes multiple instructions at the same cycle. According to the decoding result, we know the value of the source operands of each instruction, and there are instructions that would have dependency problems and would affect the result of reuse test. We would find out these problems by classifying them into different classes and solve them if they would affect the reuse test. If the reuse test is not affected, then the instruction reuse can be done as the usual way, else instruction reuse should be fixed to fit the situation of each cases.We have experiments on the replacement policy to check whether the usage of the RB can be increased. If the usage rate is higher, then the total instruction count can be reduced. Experimental results show that there is little difference, but it still can be viewed as a reference.We found that the instruction count can be reduced from 10% to 20% by employing mechanism we proposed, and the speedup by total clock cycles is a little less than that of instruction count, but it is still significant. There are other issues like hardware costs should also be taken into consideration in our future work.