以暫存器參考增進分支目的預測

Abstract

對於現今的超純量管線處理器而言,分支指令一直是個執行能力上的瓶頸, 因為分支指令會中斷管線中指令流的穩定進行.為了解決這個問題,各種分 支預測的策略被提出來且其中的一些策略可以達到滿高的預測準確度.分 支預測的問題可以被分成兩個部份:分支的方向和分支的目的.對於分支方 向的問題,經常被討論的一個利用兩個分支歷史層次來做預測的分支預測 器可以達到不錯的預測結果.對於分支目的的問題,則有一般被使用的分支 目的緩衝器架構和最近被提出來的利用目的儲存的預測策略可以供處理器 利用.目前分支方向的預測準確度已經可以達到 90%至99%的正確性了.然 而,對於分支目的預測的準確度通常無法像預測分支方向的準確度一樣高 卻也是個不爭的事實.在這篇論文中,我們提出了一個新的分支預測機制來 嘗試提昇分支目的的預測準確度.這個機制會去參考到暫存器檔案的內容, 然後根據其內容來作分支預測.我們延伸了傳統的分支目的緩衝器架構以 記錄每一個分支指令的來源暫存器為何.這項資訊會被用來指出暫存器檔 案中哪些暫存器會被參考到.另一項對於分支目的緩衝器的延伸是用額外 的空間來存放分支目的.根據這些延伸,對於每一個分支指令將會有兩個以 上的分支目的存放區.而要從這些被儲存的分支目的中選擇一個出來當作 預測的分支目的,我們會將暫存器的值雜湊之後使用其結果產生一個索引 來作選取的動作.在這篇論文中我們是用 SimpleScalar 這套工具來模擬 我們的設計.我們將我們提出的策略與一個基本的分支預測模型在 SPEC95 的標竿程式上面做比較,結果顯示我們提出的預測機制可以得到較好的效 果.對於各個不同的標竿程式,分支目的預測度的平均提昇程度大約可以從 1% 到 9% .此外,我們提出的這個新的預測方法還有另一個優點:根據實 驗,我們可以用較少的硬體來達到較高的預測準確度. Branch insrtuctions are always the performance bottleneck of modern pipelined superscalar processors.Branch instructions can interrupt the steady flow of instruction stream in the pipeline.To resolve the problem,various branch prediction schemes have been proposed and some of these schemes can achieve high prediction accuracy. The problem of branch prediction can be divided intotwo parts:branch directions and branch targets. For branch directions,the frequently discussed two-level branch predictor has an excellent performance. For branch targets,the common BTB-based mechanism and the recently proposed target cache scheme are used.Now the accuracy of predicting branch directions can achieve 90%~99% correct prediction. However,there is a fact that the accuracy of branch target prediction is usually not as high as the accuracy ofbranch direction prediction. In this thesis,we propose a new branch prediction mechanism to attempt to increase the prediction accuracy of branch targets.This mechanism will refer the register file and make predictions according to the register contents.We extend the traitional BTB to record the source registers for each branch instruction.This information is used to indicate which registers in the register file will be referred.Another extension to the BTB is the extra storage for storing branch targets. According to these extensions,there will be more than one target buffer for each branch instruction.To select a target among these buffered targets,we hash the register values and use the result toform an index. We simulate our design using the SimpleScalar tool set.We compare our scheme with a basic predictor model on some of the SPEC95 benchmarks.The simulation results show that the proposed prediction mechanism outperforms the basic preditor model. The average improvement on prediction accuracy of branch targets ar 1%~9% for different benchmarks.In addition, from our experiments we obtain an advantage of this newly proposed prediction scheme that we can use less hardware to get higher accuracy.