藉由提早產生分支目標減少分支目標緩衝器記憶體使用量及耗電

Abstract

現今的處理器設計，趨向於同時注重效能的增進以及省電能力。在製程技術的演進之下，積體電路中的靜態漏電(leakage power)問題日顯嚴重。實驗數據指出，在70奈米的製程下，處理器中多於60%的耗電來自於靜態漏電。而造成靜態漏電最主要的元件便是晶片上的記憶體(on-chip memory)，如分支目標緩衝器(Branch Target Buffer, BTB)及快取記憶體系統(cache memory system)等。 在這篇論文所發表的設計中，我們提出以使用算術運算單元(arithmetic unit)以及存取小型緩衝器(buffer)的方式，減少分支目標緩衝器的記憶體使用量和耗電。概念上，此方法是以小量的動態耗電(dynamic power)換取大量的靜態漏電。藉由提早產生分支目標(early target address generation)，原本必須存放於分支目標緩衝器中的資訊量可望大幅度地減少。此方法可完全不造成任何的效能下降，甚至有機會得到可觀的效能增進。實作提早產生分支目標機制，我們發現程式中超過77%的分支將不再需要存放於分支目標緩衝器中。此結果幫助我們減少了超過75%的分支目標緩衝器記憶體容量，同時減少了超過60%的分支目標緩衝器耗電。

Modern processor designs focus on both higher performance and lower power consumption. As the evolution of process proceeds, static power consumption grows dramatically. It has been shown that under 70nm process, more than 60% of the total system power is statically consumed. And large on chip memories like Branch Target Buffer (BTB) and Cache systems are held most responsible for such leakage. In this thesis, we proposed a method of exercising arithmetic unit and accessing small-size buffers to reduce the storage and power consumption of Branch Target Buffer (BTB). The idea is to reduce a large amount of static power by adding relatively small amount of dynamic power overhead. By performing an early branch target generation, information necessarily stored in BTB can be significantly lessen. The approach proposed suffers strictly no performance degradation, and can even deliver noticeable system performance improvement. With early branch target generation, more than 77% of the branches no longer need to reside in BTB. Leads to an approximately 75% of BTB storage reduction, and more than 60% of BTB power reduction.