低電耗分支目標緩衝器

Abstract

本研究針對處理器中常見的動態分支預測機制---分支目標緩衝器，進行省電 設計。一般的分支目標緩衝器是在每次抓取指令時進行存取，並由其結果決定下 次從那個位址抓取指令。但由於分支指令只佔了總指令數的一小部份，因此大部 份分支目標緩衝器的存取動作都是不必要的，於是我們可以籍由減少不必要的存 取來達到省電的目的。我們藉由程式執行時，記錄下各分支指令的位置來決定何 時應該去存取分支目標緩衝器，並且以省電成效及效能影響兩個標準來評估我們 的設計。實驗結果顯示這個設計可以在只對效能造成很小影響的情況下有效的節 省能源消耗。

This research reduces power consumption of branch target buffer (BTB) --- a commonly used dynamic branch prediction component. Conventional BTB is looked up while instruction fetcher is fetching an instruction. The result returned from BTB tells instruction fetcher the address of the next instruction. Since branch instructions occupy a small portion of total executed instructions, most BTB look-up operations are only waste power. We can reduce its power consumption by reducing useless BTB look-up counts. By recording the positions of branch instructions during run time, we can determine what time should instruction fetcher perform BTB look-up operation. This design is evaluated by two metrics: energy consumption and performance loss. The experimental result shows this design effectively saves energy consumption with only a little performance loss.