使用邊緣掃瞄標準電路於自我硬體模擬微處理器的設計

Abstract

由於微處理器執行的速度愈來愈快，使得硬體模擬器（ICE）在設計 上的複雜度增加，且設計成本也相當地昂貴。因此，對於微處理器本身能 執行硬體模擬功能的需求也日益增加。具有硬體模擬功能的微處理器稱之 為，自我硬體模擬微處理器。然而，在現今的微處理器中，仍很少見到此 設計。另一方面，邊緣掃瞄標準電路已成為微處理器中的標準設計，若將 邊緣掃瞄架構應用在自我硬體模擬設計上，可同時達到系統發展與測試的 功能。在這篇論文裡，將探討的問題包含硬體模擬電路的設計、與邊緣掃 瞄架構如何支援硬體模擬，最後並提出設計時的原則與方針。首先，在一 普遍的、管線式微處理器架構假設下，訂定自我硬體模擬微處理器架構。 然後配合此架構、與基本硬體模擬指令的特性，歸納出基本硬體模擬所需 的硬體單元，並且依據各硬體單元的需求，建構出支援自我硬體模擬的邊 緣掃瞄架構。最後，利用一實際的微控制器設計為例，根據整理出的設計 原則與方針，對此微控制器加入硬體模擬電路，實作了一顆具有硬體模擬 功能的微控制器，來驗證本論文提出的方法。 As the clock rate of microprocessors gets higher and higher in recentyears, it is more and more difficult to design an In- Circuit Emulator of a microprocessor. On the other hand, because of the rapid progress of VLSI technology, most contemporary microprocessors contain millions of transistors. Therefore, embedding the emulator functions inside a micro-processor is a promising option. We call this kind of microprocessors self-ICE microprocessors. However, they are not prevalent in current microprocessor designs. On the other hand, most microprocessors possess the IEEE 1149.1 Boundary Scan architecture to support a standardized serial scan path through the I/O pins. In this thesis, we employ the boundary scan architecture to support the design of the self-ICE micro-processor. A self-ICE microprocessor design mainly consists of three problems: microprocessor architecture modifications, on-chip emulator supports, and boundary scan supports. Design solutions to each problem will be developed and design guidelines will be summarized. Moreover, an example self-ICE micro-controller will be implemented to demonstrate our methods. The example self-ICE uses 10% more chip area than one without the self-emulation functions.