有關SA-110微處理器算術邏輯單元部分的設計與製作

Abstract

本論文探討的是SA-110微處理器的算術邏輯單元可能的內部架構， 並以硬體描述語言實現所定義出的架構。SA-110微處理器基本上是一顆管 線化簡化指令集中央處理器(pipelined RISC CPU)，它的管線階層有五層 。我們嘗試從指令集中各個資料處理指令所表現的微運算，歸納推導出整 個算術邏輯單元的微架構。而歸納得知SA-110微處理器算術邏輯單元內的 功能單元包括三大部分：算術邏輯運算單元(arithmetic logic operation unit)、移位單元(shift unit)和乘法單元(multiply unit)， 其中算術邏輯運算單元負責執行算術運算類指令及邏輯運算類指令，移位 單元負責執行移位╱旋轉類指令，至於乘法指令則可以由乘法單元單獨執 行或與算術邏輯運算單元合作執行。論文中將詳細介紹各個功能單元的內 部架構並將所得的結果用Verilog(r) HDL語言描述，而最後獲得的程式會 再和控制單元整合，以驗証所提出的組織架構達到與SA-110微處理器指令 執行的相容性。 This thesis discusses the organization of the ALU of the SA-110microprocessor and we describe the organization in hardware des-cription language. We construct the ALU by analyzing the micro-operations of the data processing instructions in SA-110 micro-processor instruction set. SA-110 microprocessor is a pipelined RISC CPU, there are five stages in the pipeline. There are threebasic functional units we have constructed in the ALU: arithmeticlogical operation unit, shift unit and multiply unit. The exe-cution of the shift instructions is in the shift unit; the execution of the multiply instructions is in the multiply unit and the execution of the arithmetic and logical instructions isin the arithmetic logical operation unit. This thesis includes the detail introduction of the organization of the functional units and we describe them in Verilog(R) HDL. These programs were integrated with the control unit of the SA-110 micro-processor also.