適用於多處理機系統之高效能疊流式單邊縱橫交換鍵

Abstract

本論文提出一個高效能疊流式單邊縱橫交換鍵以適用於共享記憶體之多處 理機系統。我們所提出的交換鍵是基於無阻塞之單邊縱橫交換鍵，並多加 一個輸出入埠以供階層式叢聚之用。此交換鍵在讀取交易處於等待資料時 ，將其匯流排使用權移轉給其它的處理機。此種設計方式能有效減少記憶 體衝突而造成系統效能下降之情況。在本設計中，交易採用疊流方式並分 為五個相位：管理、需求、等待、回應及完成。在每個周期，管理相位依 可用匯流排數目分配匯流排使用權。仲裁器也採用疊流式設計並分為三個 階段：優勝選擇、相位控制及錯誤控制，以配合交易疊流化之設計。此仲 裁器基於優先權法則並避免饑餓情況以仲裁匯流排使用權。另讀回交易具 有高優先權，以避免整體交易時間過長。藉著重疊多筆交易，此疊流式交 換鍵比無疊流式交換鍵有較高的匯流排產量。我們以Verilog硬體描述語 言描述並模擬疊流式單邊縱橫交換鍵。實驗結果驗証了本設計之正確性， 並顯示我們所提出的疊流式縱橫交換鍵能有效增加產量。本論文的貢獻在 於設計一個有高產量並可靠的單邊縱橫交換鍵，以適用於效能日益提升的 多處理機環境中。 In this thesis, a high performance pipelined one-sided crossbarswitch is presented for shared memory multiprocessor systems. Theproposed switch is based on a non-blocking one-sided crossbarswitch with an extra I/O port for hierarchical clustering. Theproposed pipelined switch design releases the ownership of a bus toother processors when a read transaction is waiting for returndata. This design can effectively reduce the effect of memorycontention that degrades system performance. In our design, a transaction is pipelined and divided into five phases:management, request, wait, response, and completion.At each cycle, the management phase grants requests depending onthe number of available bus-lines. The arbiter is also pipelinedinto three stages: winner selector, phase controller,and error controller, which is a structure pipeline to matchthe transaction pipeline. The arbiter uses a priority schemewithout starvation to arbitrate bus ownership. The read backtransaction has high priority so that the overall transactionlatency will not be too high. By overlapping transactions, theproposed pipelined switch can increase the bus throughput incomparison with the non-pipelined switch. We have described and simulated the pipelinedcrossbar switch using Verilog. Experimental results validate ourdesign and show that the proposed pipelined switch scheme caneffectively enlarge the throughput of the one-sided crossbarswitch. The contribution of this work is designing a highthroughput and reliable pipelined one-sided crossbar switch tomatch high performance multiprocessors.