分散式擊倒非同步傳送模式交換系統之設計、性能評估及錯誤診斷

Abstract

本論文提出一種無阻塞非同步傳送模式交換機模組。此交換機模組採 用輸出 及輸入緩衝器，並可擴充成大容量交換網路。如果封胞長度 為64個位元組且每個 輸出埠有三條鏈，則此交換機模組可達128個輸 出入埠。因此利用此交換機模組 則能組成16384個輸出入埠之交換網 路。而此交換網路只需用三種超大型積體電 路晶片來完成。另外經 過稍微修改此交換機模組更可提供多點傳播之服務。因此 多點傳撥交 換網路之設計及路由選擇本論文亦有詳細解說。 本論文所提出之交換機模組是由分散式擊倒交換機修改而成。當輸入埠有 封 胞時必定送出封胞到交換機中。如果此封胞在交換機中贏得競爭結 果，則此封胞 可達到目標輸出埠，否則就回到其它輸入埠等下一封胞 時槽到達時才送出。我們 採用優先權方式來防止封胞順序之破壞。如 果此封胞在交換機中競爭超過多次之 失敗，則此封胞將被丟棄。為了 證明所提出之交換機模組具有良好之性能，吾人 採用電腦模擬之方法 來完成性能之評估。結果證明本交換機模組具有良好之性能。 系統之穩定度必需要具有錯誤容忍能力。因此必需能檢測及查出錯誤的地 方。 故本論文提出一種有效的錯誤診斷方法來檢測及查出交換機模組中 之交換元 件錯誤的地方。為了能有效診斷錯誤的地方，交換元件 之設計亦做稍微的修改。 因此使得我們的診斷程序只需兩個程序就可 查出大部份之錯誤發生所在。如果兩 個程序無法診斷錯誤發生所在， 則採用二元搜尋法就可把所有可能發生錯誤的地 方找出來。 然而在非同步傳送模式交換系統中，其週邊模組亦佔有重要的角色。因此 本 論文提出兩種超大型積體電路晶片供非同步傳送模式交換機之週邊 模組使用。一 種是採用內容讀取式記憶體之封胞頭轉換及話務量控制 晶片。此晶片可用於網路 與用戶介面間之封胞頭轉換、話務量之監控 及收集等功能。除此之外，一種話務 量可控制之封胞組合與分解器晶 片更可提供未來各種用戶端之終端機使用。 In this dissertation, a nonblocking ATM switch module with input andoutput buffer for constructing a very large scale ATM switching networkis proposed. The maximum size of the proposed ATM switch module is limitedto K x K where K=(CL x 8)/(L+1) and CL and L denote the cell length and thenumber of links per output port, respectively. If CL = 64 octets and L = 3,the size of the proposed ATM switch module can be up to 128 input-output ports.Using this ATM switch module, a 16,384 x 16,384 ATM switching network can beobtained based on the three-stage Clos- type interconnection. The proposed ATMswitch module can be implemented by three types of fully customer VLSI chips.With a little modification, the proposed switch can provide multicast services.A three-stage multicast switching network is also designed. Furthermore,multicast routing algorithms such as call setup and call release proceduresare presented for our proposed switching network. The proposed ATM switch module is a modified version of an existingdistributed-knockout-switch. In the proposed ATM switch module, an input portwith a nonempty queue always sends a cell to the switch at the beginning ofeach time slot. The cell sent out from an input port reaches either itsdestination output port (if it wins the contention) or a different input port(if it loses). A priority scheme is adopted to preserve service-cell sequencing.A cell is discarded if it loses a predetermined number of consecutive contentions. Simulations are performed to evaluate the proposed ATM switch module underboth uniform and hot-spot nonuniform traffic models. For achieving fault tolerance, we present an efficient fault diagnosisprocedure to detect, locate, and identify the fault type of single switchelement faults for the switch element array of the distributed-knockout-switch.The proposed fault diagnosis procedure can also be used in the diagnosis ofthe proposed ATM switch module. To facilitate fault diagnosis, the operationof switch elements is slightly modified. Our diagnosis procedure can locatemost single switch element faults in two phases. Faults which cannot belocated in two phases can always be located in a third phase. Binary searchalgorithms are developed to locate some kinds of single switch element faultsin the third phase.ATM peripheral modules play an important rule in ATM systems. In this dissertation,a CAM-based header translation and traffic control chip is designed for theATM header translation, and traffic policing and gathering for every VPI/VCI.This chip can be used in the implementations of user network interface (UNI)and network network interface (NNI) for ATM systems. Besides, a trafficcontrollable cell assembler and disassembler chip is designed for implementationof a CPN in future B-ISDN applications.